This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively. The direct count is realized by the 350 M clock and the tapped delay line is constructed by the CARRY4 block. The ones-counter encoder is used to convert the thermometer code with bubble errors into binary code, which is applicable to all the FPGA chips. This work not only explains the schematic of the ones-counter encoder, but also shows how to configure it. Owing to the inconsistency of delay elements caused by process, bin-by-bin calibration is utilized to improve the differential nonlinearities (DNL) and integral nonlinearities (INL) of the TDC. A novel method was developed to compensate the influence of voltage and temperature. As the delay elements vary with voltage and temperature, a frequency counter is used to extrapolate and compensate its effect on the delay line. All of the above strategies use online calibration and improve the precision and sampling rate of TDC. The experimental results show the least significant bit (LSB) achieves 17.4 ps, the DNL is within [−0.90, 1.67] LSB, and the INL is in the range of [−1.90, 3.31] LSB.

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm² and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

This paper introduces a Fully-Static, Contention-Free Single-Phased-Clock Flip-Flop for IoT devices. The design objectives are accomplished through three main components. Firstly, the elimination of invalid toggling of internal nodes significantly reduces power consumption. Secondly, a Fully-Static and a Contention-Free structure are achieved by eliminating floating nodes and contention paths, respectively, enhancing robustness. Lastly, area is reduced through logic merging and topology compression. This Flip-Flop is implemented in a 28nm process. Post-simulation results indicate that, at 0.9V, 1GHz and activity rate of 10%/20%, dynamic power of this design is only 0.44μW/0.88μW, resulting in 86.95%/76.44% power reduction compared to traditional MSFF. This design focuses on static power. Static power of this design achieves 0.07nW/0.77nW at 10MHz, 0%, 0.4V/0.9V, 98.91%/97.59% less than MSFF. 10K Monte Carlo simulation confirms that this design maintains 100% functional integrity within the voltage range of 0.4-0.9V. Layout results indicate this design achieves an extremely low area.

The authors wish to correct the following errors in the original paper

The relentless growth of artificial intelligence of things (AIoT) applications has tightened sub-milliwatt powerbudget constraints on embedded vision systems. To address this challenge, this brief presents the first brain-inspired intelligent vision sensor (BIVS) based on a novel spiking processing-insensor (PIS) architecture that efficiently converts captured pulsewidth-modulation (PWM) image data into real-time sparse spike features for subsequent intelligent processing, offering an attractive balance between computational accuracy and energy efficiency. A 126 126 BIVS is designed in 180nm CMOS technology and consumes 66.9μJW at 661fps with a resulting efficiency of 5.02 TOPS/W and FoM of 6.37 pJ/pixel/frame. It also achieves a spike feature map accuracy of 99.73% on the MNIST dataset and a classification accuracy of 99.05% when coupled with a simplified spiking convolutional neural network (SCNN).