Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

The rapid development of microfluidic technology has increased the demand for the integration of driving circuits in the microfluidic devices. We have proposed a novel on-chip electroosmotic (EOF) micropump integrated with a high-voltage (HV) generator. The HV (49.8 V) generator is based on a Dickson charge pump, which is fabricated on a silicon-on-insulator (SOI) substrate by the standard CMOS process, and the isolation is achieved by MEMS post-processed deep trench isolation. The size of the 49.8 V generator is 425x353 μ m². The HV required for the successful operation of the micropump was generated by the integrated driving circuit with a low-voltage power supply. The maximum flow velocity and flow rate of the proposed EOF micropump were measured as 137 μ m/s and 167 nL/min, respectively when it was driven by the integrated 49.8 V generator. The efficiency of the micropump is demonstrated by comparing it with the previously reported micropumps. The proposed integration technique is reliable and effective, and potentially boosts the practical applications of lab-on-chip devices. [2019-0206]

Thinning silicon wafers for stacking in limited space is essential for the 3-D integration (3D!) technology of semiconductors. Due to the lack of research on the mechanical properties of thinned silicon wafers, it is difficult to assess and improve the mechanical reliability of 3D! semiconductor devices. This article reports the effects of thickness and crystallographic orientation on the tensile properties, such as Young's modulus, elongation, and strength, of the thinned silicon wafer. Tensile properties of a {100} silicon wafer are measured using a direct tensile testing system, where a digital image correlation method is adopted for accurate strain measurement. Femtosecond laser patterning for accurate shape control is used to fabricate dog-bone-shaped specimens with various thicknesses and crystallographic orientations. The effect of crystallographic orientation is investigated for (110), (320), (210), and (100) orientations. The Young's modulus of each orientation closely matches the theory of anisotropic elasticity. The surface energy ratios between crystallographic planes are calculated using fracture mechanics analysis. As the thickness decreases from 100 to 10 μm, the elongation and strength increase threefold, while Young's modulus is constant along the (110) direction. The strength results are analyzed with a Weibull statistical size effect model, where the Weibull modulus is calculated to be 2.35, which correlates strength only with thickness variation. Using this value and the Weibull size effect model, the expected strength of specific thickness can be calculated easily without additional experiments.

Crack formation due to thermomechanical stresses generated by a dielectric polymer thicker than 20 µm and by that with high modulus during the bumpless chip-on-wafer (COW) process has been investigated. According to the stress simulation, thermal stresses increase with polymer thickness where the stress value ranges from 100 to 200 MPa for benzocyclobutene (BCB)-based resin. Thermal stresses in the hybrid structure using epoxy-based resin and BCB-based resin were calculated to be less than 100 MPa. Thus, the reduction of the thicknesses of the polymer as well as the Si chip was found to be effective in avoiding crack formation in the COW structure. Moreover, to investigate the crack driving force, the energy release rate (ERR) was calculated. The crack propagates toward the Si chip corner and the result is consistent with the experiment. On the COW structure, a thin Si chip and a low-modulus polymer expand the process window.

This article proposes a 3-D-based redundancy scheme for the stacked dynamic random-access memory (DRAM) systems, which enables highly efficient productivity with the wafer-on-wafer (WOW) technology. Vertically replaceable block scheme and redundantly added wafer stack(s) are the keys of this technique. Memory bank replacement of the vertical combinations is taken into consideration. Random defect yield loss, which is a fundamental barrier for both the WOW technology and the leading-edge technologies, is dealt with in this study. Not only 4, 8, and 12 layers, but also 17 (16+1), 25 (24+1), and 33 (32+1) layers can be targeted. Therefore, this technique makes the WOW technology as another system scaling enabler.