Integrated 10 /spl mu/m thick poly-SiGe gyroscopes are processed on top of an 8" standard 0.35 /spl mu/m CMOS wafer with 5 metal levels by using an advanced plasma-enhanced chemical vapor deposition multi-layer technology. The gyroscopes are free-moving with Q-factors for the drive mode up to 10000 at the pressure of 0.8 mTorr while the CMOS chip is fully functional.

The integration of lightweight symmetric encryption is becoming increasingly widespread in very low-power Internet of Things applications, with the rapid emergence of very low energy block and stream ciphers in portable and wireless systems. Trivium is one of the lightweight stream ciphers shortlisted for the hardware profile of the eSTREAM project. This paper describes low-power multiradix Trivium implementations based on the use of parallelization techniques to reduce dynamic power consumption. The low-power Trivium designs were implemented and characterized in TSMC 90 nm to compare area resources and power reduction. The implementation results show that our proposed designs offer dynamic power savings of 31%–45% with radix-1 and radix-2 when compared with the standard Trivium, and 15% with radix-8. There is no improvement, however, with radix-16.

This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D magnetometer for space applications, with a significant reduction in mass and volume while maintaining a high sensitivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances and a rad-hard mixed-signal ASIC designed in a standard 0.35 μm CMOS technology. The ASIC performs sensor-signal conditioning and analogue-to-digital conversion, and handles calibration tasks, system configuration, and communication with the outside. The proposed system provides high sensitivity to low magnetic fields, down to 3 nT, while offering a small and reliable solution under extreme environmental conditions in terms of radiation and temperature.

The design of mixed-signal ASICs for space requires a detailed knowledge of the behaviour of the technology to be used in an environment imposing radiation levels and temperatures beyond those found in standard applications. Commercial foundries providing standard CMOS technologies do not usually have or make available data on the behaviour of their devices under those conditions. Instituto de Microelectrónica de Sevilla and Universidad de Sevilla (IMSE-USE) have started a long term collaboration with the Spanish Instituto Nacional de Técnica Aeroespacial (INTA) to extend its experience on mixed-signal design to the field of ASICs for space applications. The assessment of a commercial (austriamicrosystems) 0.35 μm CMOS technology is a first step towards the development of a mixed-signal design methodology, including an RHBD digital library suitable for use in space conditions.

Attacks on cryptocircuits are becoming increasingly sophisticated, requiring designers to include more and more countermeasures in the design to protect it against malicious attacks. Fault Injection Attacks and Differential Fault Analysis have proven to be very dangerous as they are able to retrieve the secret information contained in cryptocircuits. In this sense, Trivium cipher has been shown to be vulnerable to this type of attack. This paper presents four different fault detection schemes to protect Trivium stream cipher implementations against fault injection attacks and differential fault analysis. These countermeasures are based on the introduction of hardware redundancy and signature analysis to detect fault injections during encryption or decryption operations. This prevents the attacker from having access to the faulty key stream and performing differential fault analysis. In order to verify the correct operation and the effectiveness of the presented schemes, an experimental system of non-invasive active attacks using the clock signal in FPGA has been designed. This system allows to know the fault coverage for both multiple and single faults. In addition, the results of area consumption, frequency degradation, and fault detection latency for FPGA and ASIC implementations are presented. The results show that all proposed countermeasures are able to provide a fault coverage above 79% and one of them reaches a coverage of 99.99%. It has been tested that the number of cycles for fault detection is always lower than the number of cycles needed to apply the differential fault analysis reported in the literature for the Trivium cipher.

This work presents experimental results for the single-event effects characterization of a commercial (Austria Microsystems) 0.35 μm CMOS technology. It improves and expands previous results. The knowledge gained is being applied in the development of a RHBD digital library.