In this paper, a 60-GHz phased array with compact symmetric hybrid feeding network in low temperature co-fired ceramic (LTCC) technology is proposed. To improve the bandwidth and cross polarization level, a magnetoelectric (ME) dipole with a strip and 5 pairs of slots is designed. Meanwhile, a theoretical model is developed to provide physical insight into the working mechanism of the ME dipole element. To reduce the feeding loss and the element gain variation in the phased array, a symmetric hybrid microstrip (MS)/substrate integrated waveguide (SIW) feeding network is proposed. The ME dipole element achieves a measured |S ₁₁ |<-10 dB and a stable gain of 4.6±0.7 dBi from 55.3 to 67 GHz. By combining the ME dipole element and the hybrid feeding network, a 4×4 antenna in package (AiP) phased array based on four 2×2 scalable subarrays is proposed. The total dimension is 14.75 mm ×14.75 mm×0.855 mm. The measured results show that fractional impedance bandwidth (|S ₁₁ |<-10 dB) of each element is ≥21.4% with ≤±0.73 dBi element-to-element gain variation and ~16.9 dBi array peak gain (including ~0.35 dB simulated interconnection loss).

This paper presents a wideband dual-polarized L-shaped probe-fed stacked patch antenna element and a 16-element phased array antenna prototype for 60 GHz antenna-in-package (AiP) applications. The primary objective is to overcome the fabrication restrictions and achieve high-performance, cost-effective AiP module using an organic multi-layer industry standard HDI process (100/230 μm minimum via/land size). A new L-shaped probe-fed structure, which functions as a monopole antenna, is implemented to enhance the bandwidth and gain performance of the stacked patch antenna. With help of the comprehensive mode analysis method, the polarization coupling mechanism is highlighted, and an isolated patch is introduced, improving the antenna polarization isolation by up to 7dB. To connect RFIC, considering limited fabrication accuracy and the AiP structure features, a broadband vertical transition structure is designed using the half-wavelength impedance transformation technique, and its working mechanism is analyzed theoretically through a distributed equivalent circuit model. Furthermore, impact of variations in key dielectric properties on important AiP characteristics is analyzed, and the process control guidelines are provided. Thermal simulations using a heatsink solution are performed to address thermal issues. For demonstration, an antenna element and a 16-element antenna array prototype are designed, fabricated, and measured. For both polarizations, measurements indicate that the proposed antenna element has a fractional impedance bandwidth (|S11|<-10 dB) of 23.1%, and its polarization isolation is better than 20 dB. Moreover, their peak gain is above 5.45 dBi. For the 16-element antenna array, each element achieves a |S11| below -10 dB from 51 to 64 GHz with 4±1 dBi gains.

A compact scalable gap waveguide (GW) phased array horn antenna with efficient decoupling network (DN) is proposed. An H-plane GW horn antenna with transverse slots-based slow-wave (SW) structures is designed as the array element. By compensating the phase error along the horn aperture, the antenna length is greatly reduced while the gain is enhanced. To suppress the strong mutual coupling between adjacent elements due to the small spacing, an efficient DN is proposed by introducing a through slot inside the intermediate sidewall between adjacent antenna elements. With this DN, an extra wideband equal-magnitude and anti-phase signal can be generated to cancel the coupling signals. Based on the contactless characteristic of the GW, the presented antenna can be extended to large-scale arrays with high reliability. An 8-element phased array antenna operating at 24-30 GHz is implemented for verification. The antenna length is reduced by 62.2% compared with the optimum horn antenna, and the mutual coupling is reduced by up to 32.7 dB with the DN. The measured array gain is higher than 19.8 dBi and the scan angle reaches ±60° with a scan loss of less than 4.5 dB.

In this letter, a miniaturized Vivaldi antenna based on fan-out wafer-level packaging (FOWLP) process with a single redistribution layer (RDL) is proposed. A step-by-step design procedure for the proposed antenna is presented. By introducing the slots and semicircular-shaped loads, its low-end cut-off frequency is extended from 35.28 to 24.04 GHz, leading to a size reduction by 31.8% when normalized to the lowest operating frequency. Moreover, a wideband low-pass coplanar waveguide to slotline transition is proposed for antenna feeding, in which a folded split ring resonator and etching periodic slots are added to reduce the transition insertion loss above 40 GHz. Prototypes of the proposed antenna and back-to-back coplanar waveguide to slotline transition were fabricated and measured. The measured return loss of the BTB transition is better than 13.4 dB from DC to 67+ GHz, and the insertion loss of a single transition is below 0.95 dB. The measured |S11| of the proposed antenna is less than -10 dB from 23 to 67+ GHz with 4.5-7.1 dBi measured gain and >84% simulated efficiency.

For satellite communication applications, this paper presents an image rejection Ku-band low noise amplifier (LNA) in a 65-nm CMOS process for the Hartley receiver architecture. To achieve high input/output linearity performance, the inductive source degenerated cascode and the capacitive neutralized common-source (CS) amplifier topologies are used in the LNA input and output stages, respectively. To achieve wideband input return loss, the minimum noise figure and high gain performance simultaneously, the inductive source degenerated cascode amplifier is co-designed with the fourth order input impedance matching network. For the image rejection purpose, a bridged-tee band-stop filter is proposed. The measurements show the LNA achieves 14.3-to-18.3 GHz 3 dB bandwidth with 17-to-20 dB power gain, 3.5-to-4 dB noise figure, 17-to-37 dB image rejection and -5 dBm IIP3. Including all pads, the chip occupies a silicon area of $1360\times 450\,\,\mu \text{m}^{2}$ and consumes 72 mW DC power.

This paper presents a temperature-insensitive wideband cryogenic amplifier for superconducting nanowire single-photon detectors (SNSPD). With a proposed folded diode-connected transistor load to realize a good device-tracking feature, the theoretical derivations the simulations and test results prove that the amplifier-gain cell has a stable gain performance over a wide temperature range, solving the issues of a lack of the accurate cryogenic device models. The amplifier achieves a gain of 26 dB from 100 kHz to 1 GHz at 4.2 K, consuming only 1.8 mW from a 1.8 V supply. With a 0.13-μm SiGe BiCMOS process, the chip area is 0.5 mm².