This article presents a fully integrated 100-GHz continuous-wave Doppler radar transceiver with the double-sideband low-intermediate-frequency (IF) architecture for mechanical vibration and vital sign detection. Fabricated in a 65-nm CMOS process, the whole radar chip transceiver consumes 262 mW with a size of 0.9 mm x 2.0 mm. Instead of utilizing a fundamental 100-GHz voltage controlled oscillator (VCO) in the chip, a push-push frequency doubler with the 50-GHz external source is adopted to drive the transceiver. Under a dedicated design on the system architecture and circuit blocks, the chip could transmit 4-dBm saturated power (Psat) over 93-105 GHz with a 40-mV 1-kHz IF carrier and achieve good I/Q performance of phase mismatch < 1° and amplitude mismatch <1 dB over 95-104 GHz. With a -36-dBm RF input from 99 to 104 GHz, the IF differential output amplitude varies from 470 to 680 mV. To validate the detection ability, a probe-station-based test setup is proposed. Benefiting from the short wavelength at 103 GHz, this radar system successfully detects the mechanical vibration of 1-μm displacement from 1.5 m, the human vital-sign signal from 2 m, and even a small bullfrog's hybrid respiratory motion from 0.6 m. To the best of our knowledge, this is the first 100-GHz CMOS Doppler radar transceiver chip with the low-IF architecture for the biological vital sign detection.

This paper presents a 28-GHz low phase noise voltage-controlled oscillator (VCO) in a 65-nm CMOS process for 5G communication applications. With the capacitive splitting and transformer feedback techniques, theoretical analysis and simulations are undertaken for the proposed oscillator, proving that its negative Gm can be enhanced over the interested frequency range and reduced at the harmonic frequencies. Moreover, the proposed oscillator startup performance is analyzed, and its tank quality factor, transient and phase noise performance are simulated. With 4-bit switch capacitors and varactors, the proposed VCO achieves a tuning range from 25.7 to 29.7 GHz, consuming 10.8 mW from a 0.9-V supply voltage. With a wideband common-source buffer, the output signal power is around 1 dBm. At 26.5 GHz, the proposed VCO achieves low phase noise of -105.8 dBc/Hz at 1-MHz offset and -130 dBc/Hz at the 10-MHz offset, respectively.

In this paper, a 60-GHz phased array with compact symmetric hybrid feeding network in low temperature co-fired ceramic (LTCC) technology is proposed. To improve the bandwidth and cross polarization level, a magnetoelectric (ME) dipole with a strip and 5 pairs of slots is designed. Meanwhile, a theoretical model is developed to provide physical insight into the working mechanism of the ME dipole element. To reduce the feeding loss and the element gain variation in the phased array, a symmetric hybrid microstrip (MS)/substrate integrated waveguide (SIW) feeding network is proposed. The ME dipole element achieves a measured |S ₁₁ |<-10 dB and a stable gain of 4.6±0.7 dBi from 55.3 to 67 GHz. By combining the ME dipole element and the hybrid feeding network, a 4×4 antenna in package (AiP) phased array based on four 2×2 scalable subarrays is proposed. The total dimension is 14.75 mm ×14.75 mm×0.855 mm. The measured results show that fractional impedance bandwidth (|S ₁₁ |<-10 dB) of each element is ≥21.4% with ≤±0.73 dBi element-to-element gain variation and ~16.9 dBi array peak gain (including ~0.35 dB simulated interconnection loss).

In this paper, we propose a new envelope detection (ED) method to reduce the analog-to-digital converters' (ADCs) sampling rate from 20 kHz to 20 Hz in a double-sideband low-intermediate-frequency (IF) continuous-wave Doppler radar. Compared with the conventional synchronous demodulation (SD) method, which typically consumes a large amount of ADC resources, the proposed ED can achieve the same results on both mechanical vibration and human vital sign detection. Meanwhile, this paper also describes in detail the hardware implementation of carrier compensation and envelope detectors to recover and extract the envelopes in the IF domain. Experiments also show that, when the IF carrier frequency is higher than 1 kHz, the signal-to-noise ratio performance of ED would be comparable to that of SD.

Two high‐gain broadband 60GHz integrated planar patch array antennas, without and with air cavity, are designed and implemented on Rogers 5880 substrate. The differential antenna structure is used to improve the signal integrity at millimetre‐wave frequencies. The antennas are co‐designed with bonding wires of which the parasitic effect is compensated using a passive network. The proposed antennas have the advantages of symmetrical radiation pattern, wide bandwidth and low insertion loss. In the measurement, a differential transmission line based de‐embedding structure is developed on silicon, mimicking the real chip packaging environment and providing reliable terminations for antennas. The measured fractional bandwidths (| S ₁₁ | < −10dB) are 13.8 and 26.2%, respectively, for the two structures without and with air cavity, including the effect of a waveguide‐to‐microstrip line transition and a branch‐line balun. Both antennas have measured gain of about 12 dBi. After de‐embedding the return loss, the measured insertion loss of the bond wire compensation network is only 0.07dB at 61GHz.