DC power distribution systems for data centers, industrial applications and residential areas are expected to provide higher efficiency, higher reliability and lower cost compared to ac systems and have been an important research topic in recent years. In these applications an efficient power factor correction rectifier, supplying the dc distribution bus from the conventional three-phase ac mains is typically required. This paper analyzes the three-phase, buck-type, SWISS Rectifier for the realization of an ultra-high efficiency PFC rectifier stage with 400V rms ac input and 400V dc output voltage. It is shown that the rectifier's mains current THD can be improved by interleaving two converter output stages. The dc output filter is implemented using an Integrated Common Mode Coupled Inductor which ensures equal current sharing and provides common mode EMI filter inductance. The necessary design equations for selecting semiconductors, magnetic core and number of turns and the EMI filter are discussed and an ultra-high efficient 8kW, 4kW/dm3 (64W/in) prototype converter using 1.2kV SiC MOSFETS is designed. Measurements confirm a full-load efficiency of 99.16% and a peak efficiency of 99.26% and the compliance to CISPR 11 Class B conducted emission limits.

For three-phase AC-DC power conversion, the widely-used continuous current mode (CCM) modulation scheme results in relatively high semiconductor losses from hard-switching each device during half of the mains cycle. Triangular current mode (TCM) modulation, where the inductor current reverses polarity before turn-off, achieves zero-voltage-switching (ZVS) but at the expense of a wide switching frequency variation (15x for the three-phase design considered here), complicating filter design and compliance with EMI regulations. We propose a new modulation scheme, sinusoidal triangular current mode (S-TCM), that achieves soft-switching, keeps the maximum switching frequency below the 150kHz EMI regulatory band, and limits the switching frequency variation to only 3x. Under S-TCM, three specific modulation schemes are analyzed, and a loss-optimized weighting of the current bands across load is identified. The 2.2kW S-TCM phase-leg hardware demonstrator achieves 99.7% semiconductor efficiency, with the semiconductor losses accurately analytically estimated within 10 % (0.3W). Relative to a CCM design, the required filter inductance is 6x lower, the inductor volume is 67% smaller, and the semiconductor losses are 2x smaller for a simultaneous improvement in power density and efficiency.

Triangular-current-mode (TCM) modulation guarantees zero-voltage-switching across the mains cycle in AC-DC power converters, eliminating hard-switching with a minor 30% penalty in conduction losses over the conventional continuous current mode (CCM) modulation scheme. TCM-operated converters, however, include a wide variation in both switching frequency and switched current across the mains cycle, complicating an analytical description of the key operating parameters to date. In this work, we derive an analytical description for the semiconductor bridge-leg losses in a TCM AC-DC converter, including the rms current and/or conduction losses, switching frequency, and switching losses. For SiC MOSFETs, we introduce a new loss model for switching losses under zero-voltage-switching, which we call “residual ZVS losses”. These losses include the constant Coss losses found in previous literature but must also add, we find, turn-off losses that occur at high switched currents. The existence and modeling of these turn-off losses are validated on the IMZA65R027M1H 650V SiC MOSFET. The complete loss model is validated on a 2.2kW hardware bridge-leg demonstrator, which achieves a peak 99.6% semiconductor efficiency at full load. The proposed, fully-analytical model predicts bridge-leg losses with only 12% deviation, accurately including residual ZVS losses across load, modulation index, and external gate resistance.

Fast charging of electric vehicles (EVs) requires isolated AC/DC converters with a wide output voltage range of 200V to 1000V. Combining a three-level Vienna Rectifier (VR) with four isolated Dual-Active-Bridge DC/DC Converter (DABC) modules and latest-generation 600V GaN technology enables very high switching frequencies of 560 kHz for the VR and up to 330 kHz for the DABCs. Hence, in this paper an ultra-compact realization of a 10 kW EV charger module with a power density of 9 kW/dm ³ (about 150 W/in ³ ), not including the coldplate, is presented. In this context, a simplified DABC modulation method and straightforward yet accurate (confirmed by experiments) loss models for the DABCs and the VR are introduced, which facilitate a thorough investigation of the optimum synergetic operation of the two stages: For the considered converter, changing the VR operating mode from conventional 3/3-PWM (where the two stages operate rather independently and hence all three VR bridge-legs operate with PWM) to 1/3-PWM (where the DABCs shape the voltage of the shared intermediate DC-link such that always only one of the VR’s three bridge-legs must operate with PWM) results in an advantageous efficiency improvement of up to about 2% over a large part of the output voltage and power range, and in a peak efficiency of more than 97%. Further, the synergetic operation of the two-stage system (VR and DABCs) is experimentally verified for the first time, confirming the modeling results and the efficiency advantage of 1/3-PWM (i.e., 95.4% vs. 95.1% at the rated load of 10 kW and with 500V output voltage). Conducted EMI pre-compliance measurements indicate that the change of the operating strategy from 3/3-PWM to 1/3-PWM only requires minor changes of the EMI filter design.

Latest research results on three-phase wide-bandgap (WBG) inverter systems with full-sinewave output voltage filtering are reported. A new soft-switching modulation scheme for two-level 1200 V SiC inverters is described. Furthermore, a new Figure-of-Merit for determining maximum multi-level (ML) bridge-leg efficiency is defined and low-voltage GaN devices are evaluated considering ML flying capacitor (FC) and multi-cell inverter structures. Finally, new integrated-filter buck-boost current DC-link inverter topologies are discussed.

Next-generation VSD systems utilize SiC MOSFET to achieve both high efficiency through reduced bridge-leg losses and high power density through an order-of-magnitude increase in switching frequency or reduction of the DC-link capacitance. These systems, however, must contend with the high voltage slew rate of these next-generation power semiconductors, especially in the context of protecting the motor from partial discharge phenomena, surge voltages from cable reflections, and unequal distribution of the voltage across motor windings. We assess the attractiveness of an external Miller capacitor across the bridge-leg power semiconductors to limit the maximum voltage slew rate in a system. To evaluate this technique, we propose a maximum dvDS/dt model, finding that the maximum turn-on slew rate occurs at ZCS. During the turn-off transition, the applied dvDS/dt saturates at a particular current. We then find a switching loss model, arriving at a piecewise-linear dependence of bridge-leg switching losses on current under dvDS/dt-limited conditions, a finding that runs counter to the widely-utilized quadratic current dependence. The proposed models are validated on a SiC MOSFET bridge-leg designed for a 10kW 800V DC-link VSD system. This SiC MOSFET bridge-leg achieves peak calculated bridge-leg efficiencies of 99.4% for a dvDS/dt limitation of 1