Single-phase inverters and rectifiers, with a DC-side voltage of 400V, achieve ultra-high-efficiency with a simple 2-level topology. These single-phase designs typically utilize a line-frequency unfolder stage, which has very low losses and essentially doubles the peak-to-peak voltage that can be generated on the AC-side for a given DC-link voltage. For three-phase applications, unfolders cannot be similarly used, and the DC-link is typically set to 800V for 230Vrms phase voltage systems. Previous demonstrations indicate that significantly more levels are required for ultra-high-efficiency three-phase converters. We determine the number of levels required for three-phase, 800V DC-link converters to reach the same efficiency as single-phase systems. For this, we derive general scaling laws for bridge-leg losses across number of levels and DC-link voltage, finding the efficiency-optimal chip area and the minimum semiconductor losses. With commercially-available semiconductors, 7-levels are required for an 800V, three-phase AC/DC converter to meet or exceed the bridge-leg efficiency of a 2-level, 400V GaN benchmark for a fixed output filter. The 2.2kW DC/AC hardware demonstrators presented here confirm the necessity of higher-complexity converters, where we show a 2-level, 400V benchmark (99.2% peak efficiency at 18.0kW/l) and a 3-level, 800V (98.8%, 9.1kW/l) and a 7-level, 800V inverter phase-leg (99.03%, 15.8kW/l).

Figures-of-merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material- and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a figure-of-merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the XFOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridge-leg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. Finally, to validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10kW photovoltaic (PV) inverter.

The increasing demand for higher power densities and higher efficiencies in power electronics, driven by the aerospace, electric vehicle and renewable energy industries, encourages the development of new converter concepts. In particular, modular and/or multi-level (M/ML) topologies are employed to break the performance barriers of state-of-the-art power converters by simultaneously reducing the system losses and volume/weight. These improvements mainly originate from the replacement of high voltage transistors, typical of two-level converters, with low voltage, e.g. 200V, devices, offering superior electric performance. Hence, two low on-state resistance silicon (Si) and gallium nitride (GaN) 200V power semiconductors are comprehensively characterized in this paper to support the multi-objective optimization and the design of M/ML power converters. First, the selected devices are analyzed experimentally determining their conduction, thermal and switching characteristics; for this purpose, a novel ultra-fast transient calorimetric measurement method is introduced and explained in detail. In the course of this analysis, an unexpected switching loss mechanism is observed in the Si devices at hand; the physical reason of this behavior is clarified and it is proven to be solved in next generation research samples, which are also characterized by measurements. Finally, the influence of the measured power semiconductors performance on the overall efficiency and power density of a typical converter is determined through a case study analyzing a hard switching half-bridge operated as single-phase inverter, i.e. the fundamental building block of several M/ML topologies. It is concluded that, in this voltage and power class, GaN e-FETs are nowadays approximately a factor of three superior to Si Power MOSFETs; however, the better heat dissipation achieved by the latter still makes them the preferred solution for higher power applications.

For three-phase AC-DC power conversion, the widely-used continuous current mode (CCM) modulation scheme results in relatively high semiconductor losses from hard-switching each device during half of the mains cycle. Triangular current mode (TCM) modulation, where the inductor current reverses polarity before turn-off, achieves zero-voltage-switching (ZVS) but at the expense of a wide switching frequency variation (15x for the three-phase design considered here), complicating filter design and compliance with EMI regulations. We propose a new modulation scheme, sinusoidal triangular current mode (S-TCM), that achieves soft-switching, keeps the maximum switching frequency below the 150kHz EMI regulatory band, and limits the switching frequency variation to only 3x. Under S-TCM, three specific modulation schemes are analyzed, and a loss-optimized weighting of the current bands across load is identified. The 2.2kW S-TCM phase-leg hardware demonstrator achieves 99.7% semiconductor efficiency, with the semiconductor losses accurately analytically estimated within 10 % (0.3W). Relative to a CCM design, the required filter inductance is 6x lower, the inductor volume is 67% smaller, and the semiconductor losses are 2x smaller for a simultaneous improvement in power density and efficiency.

Triangular-current-mode (TCM) modulation guarantees zero-voltage-switching across the mains cycle in AC-DC power converters, eliminating hard-switching with a minor 30% penalty in conduction losses over the conventional continuous current mode (CCM) modulation scheme. TCM-operated converters, however, include a wide variation in both switching frequency and switched current across the mains cycle, complicating an analytical description of the key operating parameters to date. In this work, we derive an analytical description for the semiconductor bridge-leg losses in a TCM AC-DC converter, including the rms current and/or conduction losses, switching frequency, and switching losses. For SiC MOSFETs, we introduce a new loss model for switching losses under zero-voltage-switching, which we call “residual ZVS losses”. These losses include the constant Coss losses found in previous literature but must also add, we find, turn-off losses that occur at high switched currents. The existence and modeling of these turn-off losses are validated on the IMZA65R027M1H 650V SiC MOSFET. The complete loss model is validated on a 2.2kW hardware bridge-leg demonstrator, which achieves a peak 99.6% semiconductor efficiency at full load. The proposed, fully-analytical model predicts bridge-leg losses with only 12% deviation, accurately including residual ZVS losses across load, modulation index, and external gate resistance.

Fast charging of electric vehicles (EVs) requires isolated AC/DC converters with a wide output voltage range of 200V to 1000V. Combining a three-level Vienna Rectifier (VR) with four isolated Dual-Active-Bridge DC/DC Converter (DABC) modules and latest-generation 600V GaN technology enables very high switching frequencies of 560 kHz for the VR and up to 330 kHz for the DABCs. Hence, in this paper an ultra-compact realization of a 10 kW EV charger module with a power density of 9 kW/dm ³ (about 150 W/in ³ ), not including the coldplate, is presented. In this context, a simplified DABC modulation method and straightforward yet accurate (confirmed by experiments) loss models for the DABCs and the VR are introduced, which facilitate a thorough investigation of the optimum synergetic operation of the two stages: For the considered converter, changing the VR operating mode from conventional 3/3-PWM (where the two stages operate rather independently and hence all three VR bridge-legs operate with PWM) to 1/3-PWM (where the DABCs shape the voltage of the shared intermediate DC-link such that always only one of the VR’s three bridge-legs must operate with PWM) results in an advantageous efficiency improvement of up to about 2% over a large part of the output voltage and power range, and in a peak efficiency of more than 97%. Further, the synergetic operation of the two-stage system (VR and DABCs) is experimentally verified for the first time, confirming the modeling results and the efficiency advantage of 1/3-PWM (i.e., 95.4% vs. 95.1% at the rated load of 10 kW and with 500V output voltage). Conducted EMI pre-compliance measurements indicate that the change of the operating strategy from 3/3-PWM to 1/3-PWM only requires minor changes of the EMI filter design.