This article presents a 23–28-GHz digital-controlled phase-invariant and ultralow gain error variable gain amplifier (VGA) for 5G applications. The mechanisms of gain control and phase variation in CMOS VGA based on single-level transistor structure are analyzed in detail. According to the analysis, an active cross-coupling neutralization (ACCN) technique is proposed. The ACCN technique not only compensates for phase variation, but also makes phase compensation insensitive to the process, supply voltage, and temperature (PVT) variations. For achieving ultralow gain error, an asymmetric capacitive gain resolution improvement (ACGRI) technique is adopted, which realizes a fine gain step with low control circuit complexity. Further to reduce gain error, greatly improving the accuracy and robustness against PVT of gain control is necessary. With regard to this, a current-type digital-to-analog converter (DAC) is also integrated onto the chip. The proposed VGA is demonstrated in 65-nm CMOS technology with a core chip area of 0.14 mm ² . Under 5-b digital gain control conditions, the presented VGA achieves a measured linear gain tunability range of 6.2 dB with a 0.2-dB fine tuning step. The measured root mean square (rms) phase error is less than 0.92° across 24–28 GHz with a minimum value of 0.63° at 27.8 GHz. The rms gain error is less than 0.13 dB, with a minimum value of only 0.03 dB at 25 GHz. At the maximum gain state, the proposed CS VGA exhibits a peak gain of 29.4 dB with 3-dB bandwidth of 23.5–27.5 GHz and the minimum noise figure is 4.8 dB at 26 GHz. Besides, the measured OP _1dB and OP _3dB are 6.3 and 9.6 dBm, respectively. The influence of VT variations on the phase compensation and gain tuning is also measured, and the proposed VGA exhibits strong robustness.

A variable gain amplifier (VGA) featuring wide bandwidth and low phase variation is presented for the new generation phased arrays supporting multiple-frequency bands simultaneously. In this article, the mechanism of phase variation in common-source (CS) CMOS amplifier cell is investigated in detail. As revealed by this analysis, the parasitic capacitor C $_{\text{gd}}$ and the magnetic coupling among inductors as well as parasitic capacitors in layout inducing by interconnection lines are some of the key factors that generate feedforward signal, which leads to the phase variation. The other is the inconstant input and output admittance that result in phase deviation over a wideband region. To achieve low phase variation over broadband for CMOS CS VGA, an innovative phase compensation method based on feedforward signal suppression (FSS) and impedance-invariant techniques is proposed. Specifically, the active cross-coupling neutralization topology is employed to suppress the feedforward signal generated by C $_{\text{\rm gd}}$ . Meanwhile, an isolation enhancement layout approach aiming at mitigating the inductive coupling and parasitic capacitors in layout is proposed. Besides, a control circuit based on the impedance-invariant technique is developed to minimize the impedance variation. As a result, a low phase variation VGA with broadband phase compensation is achieved. The measured gain control range is 23 dB, with a 3-dB bandwidth of 20–43 GHz and a peak gain of 15 dB. The measured phase variation is $<$ 2 $^{\circ}$ in 18–36 GHz and $<$ 6 $^{\circ}$ across 18–45 GHz. The noise figure and input-referred P $_{\text{1\,dB}}$ are 5.5 dB and $-$ 18 dBm in the maximum gain state, respectively. The measurement also shows the proposed VGA has good robustness against the variation of supply and temperature. The VGA consumes 30.8 mW from a 1.1-V voltage supply. The chip is fabricated in a standard 65-nm CMOS process and the core area is 0.34 mm $^{\text{2}}$ .

A low-cost and integration-efficient Ku -band phased array is demonstrated for satellite communication, which is package integrated with four independent 180-nm CMOS transceivers (TRXs) with on-chip antennas. To improve the integration of phased-array beamformer while considering the cost, a cost-effective packaging technique combining on-chip and printed circuit board (PCB) is proposed. In addition, an off-chip guard ring array is introduced to further optimize the gain and sidelobe suppression level. The designed CMOS TRX integrated circuit (IC) achieves a measured maximum gain of 17.6 dB with a 3-dB bandwidth of 15.5–18 GHz in the transmitter (TX) mode. The receiver (RX) mode realizes a peak gain of 19.2 dB at 16.5 GHz. With the help of the proposed techniques, the packaged four-element phased array demonstrates a measured beam steering range of $\pm$ 32 $^{\circ}$ . It provides important guiding significance for the design of the phased array with high integration, superior performance, and low cost operating in lower frequencies.

This letter investigates the mechanism of the phase characteristics versus frequency of the conventional and modified switched T-type attenuator cells in detail. According to the analysis, the optimal phase compensation interval for different topologies is revealed for the first time, which has important guiding significance for the design of ultralow phase error digital step attenuator (DSA) operating in different frequency bands. Furthermore, to verify the correctness and validity of the analysis, a $W$ -band 3-bit DSA was implemented in a standard 65-nm CMOS process. It achieves a measured dynamic attenuation range of 7-with 1-dB tuning step. With the help of the parallel-type capacitive phase compensation technique, the DSA exhibits a measured root-mean-square (rms) phase error of 1.1 $^{\circ}$ at 90.5 GHz and phase fluctuation of only 1.6 $^{\circ}$ across 85–105 GHz. Besides, the tested rms amplitude error is less than 0.6 dB. The core chip area of the designed DSA is 0.082 mm $^{2}$ . To the best of our knowledge, the effectiveness of parallel-type phase compensation technique based on switched T-type is first verified in $W$ -band.

This article presents a 22–31-GHz high-gain power amplifier (PA) with a stability–efficiency–reliability-enhanced serial–parallel current-reuse technique for 5G communications. The existing current-reuse techniques basically rely on the stacked coupling approach, which will have a risk of generating negative output impedance, resulting in potential instability and oscillation of the amplifier. Second, considering efficiency and reliability, another major problem is that they are inapplicable to power stage design, especially multiway high power. To address these issues, a novel single-level uncoupled serial–parallel current-reuse technique is proposed and applied to power stage for the first time. With this technique, the dc path of the power stage is equivalent to multiple common-emitter (CE) amplifiers in cascaded sharing the same current, and the final consumed total current is small instead of the sum of the individual ways, which can significantly alleviate the pressure on current intensity requirements, thereby enhancing the reliability, while the RF path is multiple CE amplifiers in parallel rendering both higher efficiency and stronger stability. Furthermore, a self-cancellation-based AM–PM distortion compensation technique is adopted to attain high linearity without sacrificing performance or introducing dramatic design complexity. The proposed PA with both techniques is demonstrated in a 0.13- $\mu$ m SiGe BiCMOS technology with a chip area including PADs of 0.56 mm $^{{2}}$ . It exhibits a measured peak gain of 31.9 dB with 3-dB bandwidth of 22.7–30.7 GHz. At such a high power gain, the PA is still unconditionally stable over all measured frequencies. Besides, the PA achieves a 16.2-dBm saturated output power ( ${P}_{{\text{sat}}}$ ), a 13.9-dBm output 1-dB compression point power (OP $_{{\text{1dB}}}$ ), and a 20.5% peak PAE. Without applying any predistortion, the prototype realizes a measured AM–PM distortion till OP $_{{\text{1dB}}}$ point of ${<}1^{\circ}$ and gain expansion in the linear region of ${<}0.3$ dB at 28 GHz. Modulated signal measurements are also performed at 28 GHz with 2.4-and 3.2-Gb/s symbol rates. The PA achieves 9.3-dBm average output power with $-$ 32.9-dBc adjacent channel leakage ratio (ACLR) and $-$ 24.1-dB error vector magnitude (EVM).

This article presents a physics-enhanced equivalent circuit model for high-frequency interconnections integrating ball grid arrays (BGAs) with redistribution layers (RDLs), fabricated using wide-ground coplanar waveguide (CPW) structures. Moving beyond existing models proficient in characterization of basic parameters, the core innovation lies in the establishing an equivalent circuit model that enables quantifiable calculation and early prediction of eddy current inductance. In addition, a refined method for accurately modeling the inductance within BGA interconnects is proposed. Based on this model, the scaling laws governing inductance parameters with respect to BGA pitch and the effects of varying numbers of ground bumps are also discussed. The proposed model demonstrates predictive accuracy above 92% for transmission characteristics across from 0.1 to 40GHz. Systematic validation using 15 distinct physical samples, covering diverse BGA and RDL configurations, confirms an error below 8% empirical fitting with measured data. This modeling tool significantly enhances design efficiency and reliability for millimeter-wave 3-D packaging and integration systems by providing fast and accurate simulation of critical interconnection performance.