A transformer-based high-order resonator is proposed to improve the locking range (LR) of the millimeter-wave injection-locked frequency dividers (ILFDs). The LR limitations on ILFDs are discussed, and the operating principles of the proposed high-order resonator are analyzed based on their flattened phase response. The inductive gain peaking technique and the tail current source requirement are further analyzed for low power considerations. Two chips are fabricated in a 65-nm CMOS process to implement the proposed techniques: the first one measures an LR of 62.9% from 27.9 to 53.5 GHz while consuming 5.8 mW from a 1-V power supply and the second chip achieves an LR of 62.7% from 32.4 to 61.9 GHz while consuming only 1.2 mW from a 0.42-V power supply. The best figure of merit can achieve up to 24.7 GHz/mW.

This brief presents a wideband millimeter-wave (mm-Wave) low noise amplifier (LNA) with a triple-coupled technique for multiband wireless applications. To enlarge the gain and reduce the supply voltage, a modified cascode topology exploiting a triple-coupled transformer is developed. Thanks to the transformer, the transconductance of the common-gate (CG) transistor of the cascode topology is also effectively boosted, and hence the gain is further increased. Furthermore, high-order networks, which are realized by combinations of π-and T/L-type structures or transformers, are employed to implement the input, inter-stage, and output impedance matchings. They significantly broaden the bandwidth of the circuit. The LNA is demonstrated using a commercial 65-nm CMOS process. The measurement results show that the circuit achieves a maximum gain of 28.5 dB and a 3-dB gain bandwidth of 20 GHz with 32-mW dc power consumption (Pdc). The measured noise figure (NF) and input 1-dB gain compression point (IP1dB) are 2.7 3.2 dB and -24.6 -20.4 dBm, respectively, over the entire operating bandwidth.

A compact two-dimensional (2-D) scanning multibeam array operating at 28 GHz in a substrate integrated waveguide technology is proposed, designed, simulated, and fabricated in this letter. To achieve better compactness, three-way couplers, instead of traditional Butler matrices, are applied here to form 2-D scanning beam-forming network. By doing so, the occupied area can be significantly reduced. After joining to the radiation portion, a 2-D scanning multibeam array allows for 3 × 3 beam steering in two orthogonal planes is fabricated and measured to test whether the measured results agree well with the simulation.

This article presents a 23–28-GHz digital-controlled phase-invariant and ultralow gain error variable gain amplifier (VGA) for 5G applications. The mechanisms of gain control and phase variation in CMOS VGA based on single-level transistor structure are analyzed in detail. According to the analysis, an active cross-coupling neutralization (ACCN) technique is proposed. The ACCN technique not only compensates for phase variation, but also makes phase compensation insensitive to the process, supply voltage, and temperature (PVT) variations. For achieving ultralow gain error, an asymmetric capacitive gain resolution improvement (ACGRI) technique is adopted, which realizes a fine gain step with low control circuit complexity. Further to reduce gain error, greatly improving the accuracy and robustness against PVT of gain control is necessary. With regard to this, a current-type digital-to-analog converter (DAC) is also integrated onto the chip. The proposed VGA is demonstrated in 65-nm CMOS technology with a core chip area of 0.14 mm ² . Under 5-b digital gain control conditions, the presented VGA achieves a measured linear gain tunability range of 6.2 dB with a 0.2-dB fine tuning step. The measured root mean square (rms) phase error is less than 0.92° across 24–28 GHz with a minimum value of 0.63° at 27.8 GHz. The rms gain error is less than 0.13 dB, with a minimum value of only 0.03 dB at 25 GHz. At the maximum gain state, the proposed CS VGA exhibits a peak gain of 29.4 dB with 3-dB bandwidth of 23.5–27.5 GHz and the minimum noise figure is 4.8 dB at 26 GHz. Besides, the measured OP _1dB and OP _3dB are 6.3 and 9.6 dBm, respectively. The influence of VT variations on the phase compensation and gain tuning is also measured, and the proposed VGA exhibits strong robustness.

An injection-current-boosting (ICB) locking-range enhancement technique is presented to increase the locking range (LR) of the millimeter-wave (mm-wave) injection-locked frequency triplers (ILFTs). With a transformer-based fourth-order injection-coupling network, the parallel capacitance from the injection devices is resonated out over a wide frequency range and the injection current is boosted greatly. Analytical models of the ICB-ILFT are introduced, based on which the current-boosting phenomenon is analyzed. Meanwhile, the design concepts of the ultra-wideband mm-wave ILFT are presented. With the proposed ICB technique, an ICB-ILFT is designed and fabricated in 65-nm CMOS process. With a 0-dBm RF injection source, the ICB-ILFT can be locked from 22.8 to 43.2 GHz without calibration, achieving a 61.8% LR. The power consumption is only 5.0 mW and a 9.5-dB phase noise difference is observed, which is close to the theoretical value.

A Ka-band 5-bit CMOS digital step attenuator (DSA) with low phase variations for 5G applications is presented. The attenuator cell is optimized to alleviate the phase variations of conventional switched attenuators. A tail capacitor that is connected in series with the shunt resistor is used to construct a correction network with hyperbolic function characteristics. The DSA was implemented using a 65 nm CMOS process. It has a maximum attenuation range of 31 dB with 1.0 dB steps. With the help of the tail capacitor, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.27 dB and a rms phase error less than 3.7° from 37-40 GHz, the lowest such errors ever reported. The active core layout area is 0.22 mm² (0.51 mm x 0.42 mm). It shows suitable performance for 5G applications. The DSA is integrated into a phase-/amplitude-controlling chip to constitute a 5G system.