Mingbin Yu

Dr. Mingbin Yu


Research Focus & Metrics

Academic Career Length

18Years (2009-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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6 January 2009 in IEEE Photonics Technology Letters
Verified
Journal Article
Closed access
QFQing Fang
Qing Fang
JSJunfeng Song
Junfeng Song
GZGang Zhang
Gang Zhang
MYMingbin Yu
Mingbin Yu
YLYuliang Liu
Yuliang Liu
DKDim-Lee Kwong
Dim-Lee Kwong
In this letter, a nine-channel 100-GHz arrayed waveguide grating multiplexer/demultiplexer is monolithically integrated with a Mach-Zehnder interferometer thermo-optic variable optical attenuators (VOAs) arrayed on a silicon-on-insulator platform. The on-chip transmission loss is ~ 6 dB and the crosstalk is less than -25 dB for the transverse-electric mode. The maximum modulation depths of different thermo-optic VOAs are similar, ~ 15 dB with 2.7-V bias. The frequency response of our device is fast (ges 100 kHz) for thermo-optic effect devices. The maximum power consumption of a single VOA is less than 35 mW.

4 June 2018 in IEEE Photonics Journal
Verified
Journal Article
Open access
QFQing Fang
Qing Fang
XCXiaoling Chen
Xiaoling Chen
YZYingxuan Zhao
Yingxuan Zhao
JHJuan Hu
Juan Hu
HCHua Chen
Hua Chen
MYMingbin Yu
Mingbin Yu
A 1$\times$4 loop-mirror-integrated folded silicon-photonics arrayed waveguide grating (AWG) is designed and fabricated on a SOI wafer with two kinds of thickness of silicon areas. The introducing of two silicon thicknesses benefits the design of de/multiplexing devices with an optimal performance and large fabrication tolerances. Transition structures are used to connect 220nm-thick sections with 340nm-thick areas. The folded AWG consists of a half normal AWG structure, transition structures array and loop-mirror reflector array. Each loop-mirror reflector is composed of a 1$\times$2 multimode interferometers (MMI) splitter/combiner and a bend nanowire silicon waveguide, which is designed on a 220nm-thick silicon region. The half AWG structure with arrayed waveguides is designed on the 340nm-thick section. The measured on-chip loss and crosstalk are ~ -3.5 dB and ~ -20 dB, respectively. This integration of devices on a SOI wafer with different thickness of silicon sections is a potential scheme to integrate silicon-based passive and active devices with the best performances of each device.

30 November 2011 in IEEE Photonics Technology Letters
Verified
Journal Article
Closed access
QFQing Fang
Qing Fang
JSJunfeng Song
Junfeng Song
XLXianshu LUO
Xianshu LUO
LJLianxi Jia
Lianxi Jia
MYMingbin Yu
Mingbin Yu
YLYuliang Liu
Yuliang Liu
We demonstrate a high efficiency tunable ring-resonator filter on the silicon-on-insulator platform. The fabricated device shows the characteristics of a low power consumption and an ultrafast temperature-rise response. The ring-resonator is based on ridge-type silicon waveguide with NiSi heater formed on the silicon slab region surrounding the ring. The heat generated from the NiSi heater is directly transferred to the ring resonator through the silicon slab layer. Meanwhile, the ring-resonator is suspended by removing the adjacent SiO2 layer and the underlying silicon substrate. The measured temperature-rise response time is only 1.25 μs. The power consumption for 1-nm wavelength shift is only 0.38 mW, corresponding to 4.9 mW/free spectral range. The power consumption reduces 92% as compared to a similar structure without the air-isolation trench.

30 April 2010
Verified
Conference Paper
Closed access
TLTsung-Yang Liow
Tsung-Yang Liow
Kah-Wee ANGKah-Wee ANG
Kah-Wee ANG
QFQing Fang
Qing Fang
JSJunfeng Song
Junfeng Song
YXYong-Zhong Xiong
Yong-Zhong Xiong
DKDim-Lee Kwong
Dim-Lee Kwong
By tapping on the volume manufacturing capability of the Si CMOS platform, Si photonics can potentially offer costeffective yet high performance optical interface solutions, and will be especially important in short reach applications. Numerous challenges lie ahead for monolithically integrated Si photonics. There are process integration and thermal budget constraints when monolithically integrating individual Si photonic components such as modulators and photodetectors, and also CMOS on the same chip. In this work, the CMOS-compatible monolithic integration of Si modulators and Ge-on-Si photodetectors on the same wafer is demonstrated and the details of performance optimization are also discussed. Besides process compatibility, the modulators and photodetectors should possess high efficiency and the ability to operate at low power supply voltages. The methods to achieve this are also described. The carrier depletion type Si modulators achieved high modulation efficiency and speed (Vπ.Lπ = 2.6 V.cm, 10 Gbps). At 10 Gbps, an extinction ratio of 6 dB was measured in a modulator with 2-mm-long phase-shifters using single-ended drive (VRF = 5 Vpp). Low voltage operation at 3.125 Gbps was also demonstrated using differential drive, which allowed the drive voltage to be reduced to only 1 V (VRF = 1 Vpp). Ge-on-Si photodetectors were integrated by using a selective epitaxial Ge growth process. The performance of such photodetectors was evaluated in terms of speed, responsivity and dark current for different temperatures and operating voltages. It is shown that introducing a low thermal budget post-epitaxy anneal improves the performance of the Ge photodetectors, resulting in significantly improved dark current. The responsivity and speed in the low voltage regime are also enhanced, which enhances low voltage or even short-circuit (VBias = 0 V) operation.

10 February 2011
Verified
Conference Paper
Closed access
PDF file
TLTsung-Yang Liow
Tsung-Yang Liow
QFQing Fang
Qing Fang
ALAndy Eu-Jin Lim
Andy Eu-Jin Lim
LDLiang Ding
Liang Ding
QZQing Xin Zhang
Qing Xin Zhang
DKDim-Lee Kwong
Dim-Lee Kwong
Silicon Photonics taps on the volume manufacturing capability of traditional silicon manufacturing techniques, to provide dramatic cost reduction for various application domains employing optical communications technology. In addition, an important new application domain would be the implementation of high bandwidth optical interconnects in and around CPUs. Besides volume manufacturability, Silicon Photonics also allows the monolithic integration of multiple optical components on the same wafer to realize highly compact photonic integrated circuits (PICs), in which functional complexity can be increased for little additional cost. An important pre-requisite for Si PICs is a device library in which the devices are compatibly developed around a common SOI platform. A device library comprising passive and active components was built, which includes light guiding components, wavelength-division-multiplexing (WDM) components, switches, carrier-based Si modulators and electro-absorption based Ge/Si modulators, Ge/Si photodiodes and avalanche photodiodes, as well as light emitting devices. By integrating various library devices, PIC test vehicles such as monolithic PON transceivers and DWDM receivers have been demonstrated. A challenge with Si PICs lies with the coupling of light into and out of the sub-micrometer Si waveguides. The mode size mismatch of optical fibers and Si waveguides was addressed by developing a monolithically integrated multi-stage mode converter which offers low loss together with relaxed fiber-to-waveguide alignment tolerances. An active assembly platform using MEMS technology was also developed to actively align and focus light from bonded lasers into waveguides.