The arbitrary ratio power splitter is widely used in photonic integrated circuits (PICs), for signal monitoring, power equalization, signal feedback, and so on. Here we designed a fabrication-tolerant, compact, broadband, and low-loss arbitrary ratio power splitter. The proposed arbitrary ratio power splitter was realized with an adiabatically tapered silicon rib waveguide with 70 nm shallow etches and an S i 3 N 4 waveguide. The fabrication analysis confirmed that both of them are robust to fabrication errors. 3D finite-difference time-domain simulations show a very low excess loss (less than 0.02 dB for S i 3 N 4 waveguide and 0.05 dB for Si rib waveguide), and a broadband operating wavelength range (100 nm). Good fabrication tolerance and standard critical dimensions make the arbitrary ratio power splitter compatible with the standard fabrication process of commercial silicon photonic foundries.

A 1$\times$4 loop-mirror-integrated folded silicon-photonics arrayed waveguide grating (AWG) is designed and fabricated on a SOI wafer with two kinds of thickness of silicon areas. The introducing of two silicon thicknesses benefits the design of de/multiplexing devices with an optimal performance and large fabrication tolerances. Transition structures are used to connect 220nm-thick sections with 340nm-thick areas. The folded AWG consists of a half normal AWG structure, transition structures array and loop-mirror reflector array. Each loop-mirror reflector is composed of a 1$\times$2 multimode interferometers (MMI) splitter/combiner and a bend nanowire silicon waveguide, which is designed on a 220nm-thick silicon region. The half AWG structure with arrayed waveguides is designed on the 340nm-thick section. The measured on-chip loss and crosstalk are ~ -3.5 dB and ~ -20 dB, respectively. This integration of devices on a SOI wafer with different thickness of silicon sections is a potential scheme to integrate silicon-based passive and active devices with the best performances of each device.

Polarization sensitivity is a severe problem in photonic integration devices and chips based on the high-index contrast Si/SiO ₂ system. In this paper, a broadband silicon polarization splitter-rotator (PSR) comprised of a bi-level taper and a counter-tapered coupler is proposed with a large fabrication tolerance. The measured insertion loss is lower than 0.7 dB/0.73 dB for the wavelength range from 1470 to 1580 nm with a crosstalk lower than -12.1 dB/-14.7 dB for TE and TM polarization input, respectively. By integrating the PSR with silicon arrayed waveguide gratings and germanium photodetectors (PDs) on a single chip, a polarization-insensitive wavelength-division-multiplexing (WDM) receiver is demonstrated with a polarization-dependent loss as low as 1.21 dB. High-speed operations are also achieved with clear eyes at 10 Gb/s.

We propose and demonstrate on-chip power splitters based on adiabatic rib waveguide enabling arbitrary splitting ratios on a monolithic silicon photonic platform. The devices are elaborately engineered based on adiabatic directional couplers with a trapezoid-structure in the longitudinal direction in the mode evolution region. The measurement results indicate that the proposed devices can achieve over 150 nm bandwidth for arbitrary splitting ratios of 50%:50%, 70%:30% and 90%:10%. The mode evolution footprint is greatly narrowed to below 79 µm with an insertion loss of less than 0.22 dB. The demonstrated arbitrary ratio power splitters offer a promising application prospect in high-density photonic integrated circuits.

A 32×32 100 GHz silicon photonic integrated arrayed waveguide grating router (AWGR) is experimentally demonstrated for dense wavelength division multiplexing (DWDM) applications. The dimension of the AWGR is 2.57 mm×1.09 mm with a core size of 1.31 mm×0.64 mm. It exhibits 6.07 dB maximum channel loss non-uniformity with −1.66 dB best-case insertion loss and average channel crosstalk of −15.74 dB. In addition, in the case of 25 Gb/s signals, the device successfully realizes high-speed data routing. The AWG router provides clear optical eye diagrams and low power penalty at bit-error-rates of 10⁻⁹.

We demonstrate a 3-dB power splitter optimized by an enhanced particle swarm optimization algorithm based on a curved directional coupler, with a set of silicon columns introduced into the coupling region. The proposed device exhibits compact size, low loss and low wavelength dependence in the O-band. We employ the particle swarm optimization algorithm to engineer the dispersion by designing the radius of the silicon columns automatically. The demonstrated 3-dB power splitter enabled by silicon columns in silicon-on-insulator can achieve multiple performance metrics simultaneously according to our simulation results, with a compact footprint as small as 11.9 µm, low excess loss as low as 0.04 dB and broad 3-dB operational bandwidth of 60 nm with transmission fluctuations within 0.05 in the wavelength range from 1270 to 1330 nm. This work pioneers the silicon columns in the coupling region and adopts an enhanced particle swarm optimization algorithm to optimize device properties, providing significant potential for application in large-scale PICs as well as offering a new degree of freedom in the design of power splitters.