Leadless Cardiac Pacemakers (LCP) have the potential to revolutionize Cardiac Rhythm Management (CRM). Current LCPs can only pace a single location of the heart limiting their use to patients requiring single-chamber stimulation. A Multi-node system of synchronized LCPs could be used in a significantly larger patient population. Synchronization using standard communication techniques involves high power consumption decreasing the longevity of the device. In this work, we investigate Galvanic Intra Body Communication (IBC) as a method to synchronize multi-node LCP systems. First, an accurate computational torso model was used for quasi-static simulations to estimate channel pathloss in the frequency range [40 kHz-20 MHz]. The model was then verified with in-vivo measurements using a novel experimental setup, where two LCP devices were placed in the right atrium, right ventricle and left ventricle. All channels involved in a potential multi-node LCP system were characterized. The orientation of the transducers relative to each other had a great impact on the results, with the attenuation level ranging between 55 dB and 70 dB between the best and worst orientations. The best results were achieved in the MHz range. Coupled with the fact that it does not require additional electrodes, this study suggests Galvanic IBC be superior to conventional communication methods for LCP devices. This analysis defines a methodology for galvanic IBC channel characterization for LCP systems, which is an important step for the design of efficient transceivers for IBC applications. More experiments with larger datasets are needed to bring this method to practice.

This paper proposes a fully digital calibration of timing mismatch for undersampling Time Interleaved Analog-to-Digital Converter (TI-ADC) employed in Software Defined Radio (SDR) receivers. The proposed calibration scheme employs an ideal differentiator filter, a Hilbert transform filter and a scaling factor to compute the derivative of the input in any Nyquist Band (NB). The efficiency of the proposed technique is shown using a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz. Monte Carlo simulations show SNDR and SFDR improvements of respectively, 18 dB and 21 dB over the first three NBs.

This paper studies a post-distortion correction technique applied to a nonlinear receiver. The employed technique relies on the assumption that the input signal is bandlimited and uses the signal spreading in the free energy band in order to perform the estimation. The study focuses on three points: the input distortion level impact, filter complexity and quantization. A good sizing of these key parameters is mandatory in order to have an optimized CMOS implementation.

This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.

A novel low-power wideband mixed-signal approach to linearize RF power amplifiers (PAs) is presented. The proposed mixed-signal predistorter (MSPD) is based on FIR memory polynomial (FIR-MP) model, where digital FIR filter improves the memory correction performance without any bandwidth expansion and the MP predistorter in analog baseband provides superior linearization. MSPD avoids 5X bandwidth requirement for the transmitter and the power-hungry RF components when compared to digital predistorters (DPDs) and analog-RF predistorters (ARFPDs), respectively. This makes the MSPD solution a very low-power candidate and especially attractive in the context of small-cell base stations. Extracted PA model of a commercial 1 W GaAs HBT PA is linearized over an 80 MHz signal; results prove that the FIR-MP based MSPD in ideal system-level simulations provides an improvement of 14.3 dB and 13.5 dB, in adjacent and alternate channel leakage ratio, ACLR1 and ACLR2, respectively, in comparison with FIR envelope memory polynomial (FIR-EMP) model, used in ARFPD. The impact of various non-idealities are simulated at electrical-level to derive the requirements for the integrated circuit implementation shows that a resolution of 8 bits for the coefficients and a signal path SNR of 60 dB is required to achieve ACLR1 above 45 dBc, with as little as 9 coefficients in the analog domain.

This paper presents a fourth-order discrete-time direct RF-to-digital Delta-Sigma receiver architecture for flexible receivers with a wide frequency range. The use of a current-driven passive mixer with RF feedback enables high-Q bandpass filtering and relaxes the linearity requirement of the RF amplifier. In addition, the reconfigurable passive/active loop filter offers a good compromise between power consumption, linearity, and dynamic range. The other important feature of the proposed architecture is the use of a sampling frequency that is a divisor of the LO frequency. This solves several problems such as the upmixing of quantization noise, the need to reconfigure the Delta-Sigma loop when changing the LO frequency, and the use of two independent clocks for the LO and the sampling frequency. The circuit was implemented using 65 nm CMOS technology. The I/Q Direct Delta-Sigma receiver has an RF bandwidth of 20 MHz and a sampling frequency of 400 MHz. Measurement results show a very high dynamic range of up to 80 dB with a peak SNDR of 46 dB for a power consumption of 46 mW at 800 MHz.