Red-bed argillaceous siltstone is one of main types of rocks composing unstable slopes on both banks of water diversion project from the Yangtze to Huaihe River and is prone to deterioration after subjected to drying-wetting cycle conditions during water diversion project operation. The study of the damage degradation and the constitutive relationship of rocks subjected to drying-wetting cycle process is therefore of critical scientific importance. In this paper, laboratory tests were conducted to investigate the effect of drying-wetting cycles on the mechanical properties and microstructural characteristics. The experimental results show that the microstructure of the sample surface is no longer dense and uniform and the porosity of tested samples significantly increases with drying-wetting cycles increasing. After subjected to cycles of drying-wetting, the compaction stage of the stress-strain curve becomes longer with more pronounced nonlinear features, while uniaxial compression strength (UCS) and elastic modulus drop obviously. Combined with the evolution characteristics of microstructure found as the porosity grew, UCS and elastic modulus gradually decline. Additionally, from the perspective of energy analysis, the input energy density and dissipated energy density gradually extended with the increasing strain, and the elastic energy density increased first and then declined. As the number of drying-wetting cycles increases, the energy density of samples all present linear fell. Based on the evolution of dissipated energy, a new damage model of red-bed argillaceous siltstone subjected to drying-wetting cycles was established by introducing compaction coefficient. The coefficients of determination (⁠ $R2$⁠) of the constitutive model are always greater than 0.85, indicating that the proposed model is generally in good agreement with the experimental data under different drying-wetting cycles. This paper has specific research and reference value to understand the damage evolution characteristics of red-bed argillaceous siltstone under cyclic drying-wetting.

A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.

Low-Density Parity-Check (LDPC) code is a type of forward error-correction code with excellent performance, and has been widely used in many modern communication standards. The second-generation satellite broadcasting standard (DVB-S2) and its extension (DVB-S2X) adopt a special Irregular Repeated Accumulate (IRA) LDPC code as inner coding scheme. However, due to the large block size, most of the architectures proposed so far use Random Access Memory (RAM) to store and update the encoding results, and the delay caused by address-controlled read and write operations and barrel shift during computation inevitably limits the upper bound of encoder throughput. In this paper, by extracting the periodicity of the parity-check matrix, we introduce a fast encoding algorithm that can efficiently process the multiplication of the information sequence and a large-dimensional sparse matrix, and propose an encoder architecture with low encoding delay and high throughput. The proposed architecture has been implemented and tested on a Xilinx Kintex-7 FPGA, and the result show that the encoder architecture can achieve the highest throughput of 47.5 Gbps at a clock frequency of 280 MHz.