A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.

Low-Density Parity-Check (LDPC) code is a type of forward error-correction code with excellent performance, and has been widely used in many modern communication standards. The second-generation satellite broadcasting standard (DVB-S2) and its extension (DVB-S2X) adopt a special Irregular Repeated Accumulate (IRA) LDPC code as inner coding scheme. However, due to the large block size, most of the architectures proposed so far use Random Access Memory (RAM) to store and update the encoding results, and the delay caused by address-controlled read and write operations and barrel shift during computation inevitably limits the upper bound of encoder throughput. In this paper, by extracting the periodicity of the parity-check matrix, we introduce a fast encoding algorithm that can efficiently process the multiplication of the information sequence and a large-dimensional sparse matrix, and propose an encoder architecture with low encoding delay and high throughput. The proposed architecture has been implemented and tested on a Xilinx Kintex-7 FPGA, and the result show that the encoder architecture can achieve the highest throughput of 47.5 Gbps at a clock frequency of 280 MHz.

In this paper, a simple sampling frequency offset (SFO) estimation and compensation scheme based on two phase-conjugated pilots is proposed and experimentally demonstrated in an OFDM-based underwater wireless optical communication (UWOC) system. The phase shift is obtained by simple multiplication for phase-conjugated pilots, and the results are averaged to perform more accurate phase estimation. The experimental results show that the estimation offset is limited within ±3 ppm when the SFO ranges from −1000 ppm to +1000 ppm over a 1 m tap water channel. Moreover, with the help of the proposed scheme, up to ±300 ppm SFO can be well-compensated with error vector magnitude (EVM) penalties below 1 dB after 1 m underwater transmission. In addition, the results demonstrate that, compared with the ideal case without SFO, our proposed SFO compensation scheme can provide nearly negligible bit error rate (BER) penalties in saltwater with the highly scattering property.

The high standard of communication quality in optical access networks makes forward error correction (FEC) schemes, such as LDPC, an integral part of the system. However, pipeline conflict arising from data dependencies is a common issue encountered in the hardware implementation of layered QC-LDPC decoders. This paper proposes an efficient layered decoding architecture to reduce pipeline conflicts without introducing stall cycles. It can solve some of the pipeline conflicts by flexibly reordering the processing order of inter-layer and intra-layer submatrices offline. In addition, the patch method, based on variable-to-check messages, allows for the delayed use of gains between layer iterations, which can further minimize the performance loss caused by the remaining pipeline conflicts. The experimental results on the LDPC code of the IEEE802.16 standard in the OFDM-PON system demonstrate that the proposed architecture has sensitivity improvements of 0.125 dBm and 0.375 dBm, respectively, compared with our previous work and the method described in the other work. The optimized architecture improves the reliability of the decoder and can also make a contribution to efficient PON systems.

Pipeline conflicts arising from data dependencies are a common issue encountered in the hardware implementation of layered QC-LDPC decoders. This paper proposes an efficient layered decoding architecture to reduce pipeline conflicts without introducing stall cycles, by reordering the processing order offline and using the patch method based on variable-to-check message. The experimental results on the LDPC code of the IEEE802.16 standard in the OFDM-PON system demonstrate that the proposed architecture has a sensitivity improvement of 0.125 dBm and 0.375 dBm, respectively, compared with our previous work and the method described in the other work.