Novel CMOS current mode shapers for front-end electronics are proposed. In particular, six semi-Gaussian shaper implementations based on second generation current conveyors and operational transconductance amplifiers are designed using advanced filter design techniques. Although all shaper architectures are fully integrated, they satisfy a relatively large peaking time. The topologies are analytically compared in terms of noise performance, power consumption, total harmonic distortion (THD), and dynamic range (DR) in order to examine which is the most preferable in readout applications. Design technique selection criteria are proposed in relation to the shaper structures performance. Analysis is supported by simulations results using SPICE in a 0.6 μm process by Austria Mikro Systeme (AMS).

An overview of the electric field mill sensor specifications in applications related to the measurement of the atmospheric electric field was conducted. The different design approaches of the field mill sensor interface are presented and analyzed, while the sensitivity-related parameters of a field mill are discussed. The design of a non-complex analog sensor interface that can be employed for the measurement of the electric field in both fair and foul weather conditions, such as thunderstorms, is implemented using discrete components for experimental validation and is optimized in an integrated version in terms of noise and power consumption. Advanced noise simulations are conducted in a 180 nm CMOS process (XH018 XFAB). The energy-autonomous operation of the sensor for extended periods of time is made feasible due to the low power consumption of the front-end circuitry (165 μW at 3 V) as well as the proposed intermittent style of operation of the motor. The total sensing system is low power, and its realization is simple and cost-effective, while also offering adequate sensitivity (45 mV/kV/m), making it comparable to the existing works.

A new methodology for the RF/mmWave analog design process, automation and acceleration, is presented in this work. The proposed framework was implemented so as to accelerate the design cycle of analog/RF circuits by creating a dataset in a fully automated manner and training a combination of machine learning models for the optimal design parameters’ prediction. machine learning polynomial regression was adopted to accelerate the design process, predicting the optimal design parameters’ values while genetic algorithm optimization was exploited for the dataset creation automation. To evaluate the efficiency of the proposed methodology, the framework was implemented for the design of a common source Low-Noise-Amplifier, using a 65 nm CMOS process node. The proposed methodology successfully tackles the design cycle speed-up, automation, and acceleration, utilizing machine learning prediction for the design parameters and genetic algorithm for the dataset creation automation instead of the classical, simulation-based, standard design methodology. The provided experimental results have shown the effectiveness of the proposed hybrid approach, creating very precise RF matching networks for LNA designs and achieving >$99.9\%$ wave transmission efficiency while reaching >$99\%$ accuracy on the parameters’ prediction task.