The integrated circuits employed for power management in photovoltaic (PV) energy harvesting applications are required to perform an efficient maximum power point tracking (MPPT) process for maximizing the power production of the PV source during the continuously changing atmospheric conditions. Among the alternative MPPT methods, the perturbation and observation (P&O) technique has the advantages of operational and implementation simplicity. In this article, a novel PV MPPT control system for on-chip implementation of the P&O MPPT method is presented, which, compared to the past-proposed on-chip MPPT systems, has the advantage that it is implemented based on purely digital CMOS circuits without requiring the use of complex circuits, such as multipliers, sample and hold units, or analog-to-digital converters. Therefore, it can be easily implemented on-chip with low design complexity while simultaneously retaining the high-performance features of the P&O MPPT technique. The proposed PV MPPT system has been fabricated using the XFAB XH018 0.18- μ m CMOS technology. The experimental results verify the successful operation of the on-chip PV MPPT control unit and its ability to achieve a high MPPT efficiency over a wide range of operating solar irradiation values.

This work presents a novel, fully integrated low-dropout (LDO) regulator optimized for low-power applications with a wide load current range. By utilizing dynamic biasing to improve transient response, the LDO regulator achieves impressive performance with 0.26 $\mathsf{\mu }$V/mA load regulation (LDR) and 19.92 $\mathsf{\mu }$V/V line regulation (LNR). It also features a fast 8.6 $\mathsf{\mu }$s settling time during load transitions up to 30 mA and a low quiescent current of 6.3 $\mathsf{\mu }$A. The LDO regulator maintains a 1.8 V output for input voltages ranging from 2.1 V to 3.3 V, with a dropout voltage of 100 mV and supports load currents from 0.3 mA to 30 mA over a temperature range of −40 °C to +85 °C. The design, implemented in a standard 180 nm CMOS process, offers high accuracy and efficiency, making it a well-suited solution for battery-powered systems.

In this work, a unified design methodology for front-end RF/mmWave receivers is presented, aiming to significantly accelerate the design procedure of the front-end RF blocks in complex RX/TX chain implementations. The proposed design methodology is based on optimization loops with well-defined cost functions so as to minimize the design iterations that may be encountered during specification tuning. As proof of concept, two essential RF blocks widely used in RF receivers, a low-noise amplifier (LNA) and a voltage-controlled oscillator (VCO), were designed using the proposed unified methodology with a 65 nm RF-CMOS processing node. Finally, the derived designs were compared to similar designs in the literature, proving that the proposed unified methodology is capable of synthesizing RF/mmWave LNAs and VCOs with industry-standard specifications within a significantly faster time frame.

This work presents an ultra-low-power CMOS supercapacitor storage unit suitable for a plethora of low-power autonomous applications. The proposed unit exploits the unregulated voltage output of harvesting circuits (i.e., DC-DC converters) and redirects the power to the storage elements and the working loads. Being able to adapt to the input energy conditions and the connected loads’ supply demands offers extended survival to the system with the self-startup operation and voltage regulation. A low-complexity control unit is implemented which is composed of power switches, comparators and logic gates and is able to supervise two supercapacitors, a small and a larger one, as well as a backup battery. Two separate power outputs are offered for external load connection which can be controlled by a separate unit (e.g., microcontroller). Furthermore, user-controlled parameters such as charging and discharging supercapacitor voltage thresholds, provide increased versatility to the system. The storage unit was designed and fabricated in a 0.18 um standard CMOS process and operates with ultra-low current consumption of 432 nA at 2.3 V. The experimental results validate the proper operation of the overall structure.

The integration of multi-source energy harvesting (EH) systems into silicon presents a promising avenue for powering autonomous, low-power devices, particularly in applications such as the Internet of Things (IoT), biomedical implants, and wireless sensor networks, where power efficiency and small-size solutions are crucial. This review provides a detailed technical assessment of energy harvesting schemes—including photovoltaic, mechanical, thermoelectric, and radio frequency energy harvesting—and the integration of their associated electronic circuits into silicon integrated solutions. The EH systems are critically analyzed based on their architectures, the number and type of input sources, and key performance metrics such as energy conversion efficiency, output power delivered to loads, silicon area footprint, and degree of integration (e.g., reliance on external components). By examining current advancements and practical implementations, crucial design parameters are assessed for state-of-the-art integrated silicon energy harvesting systems. Furthermore, based on current trends, future research directions are outlined to enhance EH efficiency, reliability, and scalability, paving the way for fully integrated silicon-based EH systems for the next-generation self-powered electronic devices.