In this article, a recessed source trench silicon carbide (SiC) MOSFET with integrated MOS-channel diode (MCD) is proposed and investigated by TCAD simulations. The MCD features a short channel, and the channel length could be adjusted by varying the recessed depth. Owing to the drain-induced barrier lowering effect, a low potential barrier for electrons to flow through the JFET region to the N $+$ source region is formed, which successfully eliminates the bipolar degradation of the parasitic body p-i-n diode. Besides, the recessed source trench introduces an additional depletion region and homogenizes the distribution of the OFF-state electric field. As a result, a low gate-to-drain capacitance and a high breakdown voltage (BV) are obtained. Simulation results indicate that compared with the SiC trench MOSFET with integrated self-assembled three-level protection Schottky barrier diode, a 78.7% reduction in gate-to-drain capacitance and a 24.4% improvement in BV could be achieved in the proposed SiC MOSFET.

A superjunction metal-oxide-semiconductor field-effect transistor (SJ-MOSFET) with P-base and N-pillar Schottky contacts is proposed and investigated in this article. The dual Schottky contacts form a p-type Schottky diode and an n-type Schottky diode on the surface of the device, respectively. During the reverse conduction stage, the operation of the body p-n junction diode is suppressed by the reverse-biased p-type Schottky diode, and the reverse current is fully conducted by the n-type Schottky diode. Therefore, the minority carrier injection is completely suppressed, leading to an ultralow reverse recovery charge. TCAD simulation results show that, in comparison with the conventional SJ-MOSFET, up to 95.7% reduction in reverse recovery charge could be achieved.

In this article, a novel silicon carbide double-trench MOSFET with an integrated fully depleted P-base MOS-channel diode is proposed and investigated by calibrated TCAD simulations. The proposed silicon carbide (SiC) MOSFET features a fully depleted P-base region achieved by shrinking the source trench mesa in the ${z}$ -direction. Due to the significantly reduced conduction band energy in the fully depleted P-base region, a low potential barrier for electrons to flow through the JFET region to the N ⁺ source region is formed. As a result, the proposed SiC MOSFET not only exhibits more than three times lower diode cut-in voltage than the body p-i-n diode but also successfully eliminates the bipolar degradation issues. Besides, a compact model based on Poisson’s law is developed to understand the origin of the barrier lowering effect. Calibrated TCAD simulation results indicate that the enhanced third quadrant performance would not comprise the other electric characteristics, which makes the proposed SiC MOSFET a highly promising candidate for high-frequency power applications.

A power MOSFET with P-base Schottky diode and built-in channel diode is proposed and numerically investigated in this article. The P-base Schottky diode formed by the P-base Schottky contact is in reverse series with the P-base/N-drift junction diode. Besides, by coupling the gate of the dummy MOSFET to the source, a built-in channel diode is introduced, which provides a unipolar reverse conduction current path and drastically reduces the gate-to-drain charge. When the proposed MOSFET serves as the freewheeling diode, the reverse-biased P-base Schottky diode inactivates the P-base/N-drift junction diode, so that the reverse current will be carried out by the built-in channel diode. As a result, in comparison with the planar gate power MOSFET, the reverse recovery charge and the gate-to-drain charge could be reduced by 96.9 % and 75.4%, respectively.

In this paper, a novel superjunction MOSFET with ohm contact in the termination region and dual Schottky contacts in the cell region is proposed and experimentally demonstrated. The dual Schottky contacts consisting of the N-type Schottky contact and the P-type Schottky contact suppress the hole injection in the cell region, thereby reducing the reverse recovery charge and enhancing the current density in the termination region. The high current density and the ohm contact in the termination region provide sufficient slowly extracted non-equilibrium holes during the reverse reduction period, which contributes to a significantly improved softness. Experimental results show that, in comparison with the conventional superjunction MOSFET, 66.2% reduction in reverse recovery charge and 137.5% improvement in softness factor can be obtained in the proposed superjunction MOSFET.

A novel approach to inactivate the body p-i-n diode of silicon carbide (SiC) MOSFET is proposed in this article. It features a normally-OFF JFET structure embedded medially between the two p-well regions in the z-direction. When the SiC MOSFET operates in the first quadrant, the normally-OFF JFET is pinched-off, guaranteeing the excellent fundamental performance of the SiC MOSFET. While when the SiC MOSFET serves as the freewheeling diode, the channel of the normally-OFF JFET is turned on, which provides a unipolar current conduction path with low cut-in voltage, thereby inactivating the body p-i-n diode. TCAD simulation results show that, in comparison with the double trench SiC MOSFET, the cut-in voltage and the reverse recovery charge of the proposed SiC MOSFET could be reduced by 51.6% and 52.2%, respectively.