In this article, a novel silicon carbide double-trench MOSFET with an integrated fully depleted P-base MOS-channel diode is proposed and investigated by calibrated TCAD simulations. The proposed silicon carbide (SiC) MOSFET features a fully depleted P-base region achieved by shrinking the source trench mesa in the ${z}$ -direction. Due to the significantly reduced conduction band energy in the fully depleted P-base region, a low potential barrier for electrons to flow through the JFET region to the N ⁺ source region is formed. As a result, the proposed SiC MOSFET not only exhibits more than three times lower diode cut-in voltage than the body p-i-n diode but also successfully eliminates the bipolar degradation issues. Besides, a compact model based on Poisson’s law is developed to understand the origin of the barrier lowering effect. Calibrated TCAD simulation results indicate that the enhanced third quadrant performance would not comprise the other electric characteristics, which makes the proposed SiC MOSFET a highly promising candidate for high-frequency power applications.

This paper investigates the total ionizing dose (TID) effect of the memory cell of the ferroelectric random access memory (FRAM) under electron, X-ray, and Co-60 γ ray radiation sources. An electron accelerator and an X-ray microbeam from synchrotron, which are used to simulate the given radiation environments, offer local irradiation on the FRAM memory cell. In addition, the Co-60 γ ray source provides global irradiation on the full chip of FRAM. The FRAM memory cell is proved to have a lower failure threshold for TID effect than the ferroelectric thin-film capacitor due to the performance degradation of nMOS transistor in memory cell. The failure phenomenon is studied according to the experimental results of different radiation sources, and the failure mechanism is discussed based on the technology and the characteristics of FRAM memory cell in circuit-level. The difference of device performance is also analyzed for electron irradiation and X-ray irradiation.

In this work, it is demonstrated for the first time that a negative gate voltage (V_GS) during off-state can enhance the single-event effect (SEE) hardness of the 100-V E-mode p-GaN HEMTs. When subjected to irradiation from Ta ions with linear energy transfer of 78.40 MeV/(mg/cm²), the single-event transient (SET) current peak during irradiation can be significantly decreased if a negative V_GS is applied, as opposed to using zero V_GS. Furthermore, a negative V_GS suppresses post-irradiation shifts in gate capacitance (C_G), threshold voltage (V_th) and off-state drain leakage current (I_DSS), indicating improved stability against SEE. Numerical simulations have been performed to offer a physical insight into the underlying mechanisms. It is found that a negative V_GS enables the simultaneous removal for radiation-induced holes and thus suppresses the SET current. The post-irradiation degradation of C_G, V_th and I_DSS are attributed to the radiation-induced acceptor-like traps at the Schottky junction, the AlGaN/GaN interface and the buffer layer, respectively.

In this article, an enhancement mode (E-mode) p-GaN gate AlGaN/GaN high electron mobility transistor (HEMT) with the selective regrowth (SR) AlN/AlGaN strain enhancement layers has been proposed. The novel strain engineering is used to realize 2-D electron gas (2DEG) redistribution by the polarization effect and surface electric field optimization by the electric field modulation effect. The SR AlN/AlGaN strain layers increase the 2DEG density in the access region to reduce the ON-resistance ( $\textit{R}_{\text{on}}\text{)}$ effectively. The surface electric field is also reshaped, featuring an extra electric field peak far away from the gate edge, which improves the breakdown voltage (BV). As compared with the conventional HEMT, the HEMT with the SR AlN/AlGaN strain layers features the significant specific ON-resistance ( $\textit{R}_{\text{on,\textit{sp}}}\text{)}$ improvement by 11.9% (from 2.26 to 1.99 m $\Omega $ .cm $^{\text{2}}\text{)}$ and the noticeable BV enhancement from 476 to 661 V. It is concluded that the contradiction between $\textit{R}_{\text{on,\textit{sp}}}$ and BV can be relieved by using the SR AlN/AlGaN strain layers. Meanwhile, the current collapse is suppressed effectively. The dynamic $\textit{R}_{\text{on}}$ is only 1.3 times the static $\textit{R}_{\text{on}}$ after the drain–source OFF-state stress of 480 V.

In this work, it is demonstrated that the buck converter using a GaN/Si hybrid switch can achieve an even higher power conversion efficiency than the one using a pure-GaN switch with the same ratings. By replacing one of the dual paralleled GaN HEMTs with a Si superjunction mosfet having the same voltage rating yet a slightly higher resistance, the total conduction loss, however, is significantly decreased. This is accomplished through suppressing the dynamic ON-state resistance peculiar to GaN HEMTs. Optimizing the gate timing between the GaN and the Si devices within the hybrid switch enables exceptional low-loss performance. Both device-level and system-level demonstrations are performed. The experimental results prove that the p-GaN gate HEMT/Si MOSFET hybrid switch increases the efficiency by 2% and 3%, respectively, when compared to its pure-GaN and pure-Si counterparts, at an output power of 240 W and a switching frequency of 500 kHz.