A novel low-reverse recovery charge superjunction MOSFET (SJ-MOSFET) with a p-type Schottky body diode is proposed in this letter. The device has a p-type Schottky contact on the p-pillar at the drain side. Electrons are prevented from injecting into the drain side by the p-type Schottky contact, and the total carrier concentration is greatly reduced. Compared with the conventional device, the proposed SJ-MOSFET has a lower reverse recovery charge and a larger soft factor. Simulated results show that the reverse recovery charge is reduced by 81.3% and 76.0% at 300 K and 400 K, respectively, with a metal work function of 4.5 eV. The optimized metal work function range is 4.3-4.6 eV.

In this article, a recessed source trench silicon carbide (SiC) MOSFET with integrated MOS-channel diode (MCD) is proposed and investigated by TCAD simulations. The MCD features a short channel, and the channel length could be adjusted by varying the recessed depth. Owing to the drain-induced barrier lowering effect, a low potential barrier for electrons to flow through the JFET region to the N $+$ source region is formed, which successfully eliminates the bipolar degradation of the parasitic body p-i-n diode. Besides, the recessed source trench introduces an additional depletion region and homogenizes the distribution of the OFF-state electric field. As a result, a low gate-to-drain capacitance and a high breakdown voltage (BV) are obtained. Simulation results indicate that compared with the SiC trench MOSFET with integrated self-assembled three-level protection Schottky barrier diode, a 78.7% reduction in gate-to-drain capacitance and a 24.4% improvement in BV could be achieved in the proposed SiC MOSFET.

A superjunction metal-oxide-semiconductor field-effect transistor (SJ-MOSFET) with P-base and N-pillar Schottky contacts is proposed and investigated in this article. The dual Schottky contacts form a p-type Schottky diode and an n-type Schottky diode on the surface of the device, respectively. During the reverse conduction stage, the operation of the body p-n junction diode is suppressed by the reverse-biased p-type Schottky diode, and the reverse current is fully conducted by the n-type Schottky diode. Therefore, the minority carrier injection is completely suppressed, leading to an ultralow reverse recovery charge. TCAD simulation results show that, in comparison with the conventional SJ-MOSFET, up to 95.7% reduction in reverse recovery charge could be achieved.

This paper studies the short-circuit safe operating area (SCSOA) of the conventional field-stop (FS) IGBT and the superjunction (SJ) FS IGBT, based on 1200 V-rated samples, with the help of numerical electrothermal simulations. The results show that the peak electric field influences the distribution of the temperature inside devices and plays a crucial role in determining their SCSOAs. When the doping concentration of the collector, $\text{N}_{\mathrm{ C}}$ , is low, the peak electric field exits near the collector. Both types of IGBTs have a long short-circuit time, $\text{T}_{\mathrm{ SC}}$ , which can exceed $15~{\mathrm {\mu }}\text{s}$ . $\text{T}_{\mathrm{ SC}}$ decreases with the increase of $\text{N}_{\mathrm{ C}}$ because the peak electric field transfers to near the channel. The introduction of the SJ structure weakens the peak electric field and increases $\text{T}_{\mathrm{ SC}}$ . The difference is at least 4 $\mu \text{s}$ and up to 6.87 $\mu \text{s}$ , when $\text{N}_{\mathrm{ C}}$ ranges from 2.0 $\times \,\,10^{17}$ cm $^{-3}$ to 1.1 $\times \,\,10^{18}$ cm $^{-3}$ . Besides, $\text{T}_{\mathrm{ SC}}$ of the SJ IGBT can be increased by using highly-doped pillars.

In this article, a novel silicon carbide double-trench MOSFET with an integrated fully depleted P-base MOS-channel diode is proposed and investigated by calibrated TCAD simulations. The proposed silicon carbide (SiC) MOSFET features a fully depleted P-base region achieved by shrinking the source trench mesa in the ${z}$ -direction. Due to the significantly reduced conduction band energy in the fully depleted P-base region, a low potential barrier for electrons to flow through the JFET region to the N ⁺ source region is formed. As a result, the proposed SiC MOSFET not only exhibits more than three times lower diode cut-in voltage than the body p-i-n diode but also successfully eliminates the bipolar degradation issues. Besides, a compact model based on Poisson’s law is developed to understand the origin of the barrier lowering effect. Calibrated TCAD simulation results indicate that the enhanced third quadrant performance would not comprise the other electric characteristics, which makes the proposed SiC MOSFET a highly promising candidate for high-frequency power applications.