This study conducts an in-depth evaluation of imaging algorithms and software and hardware architectures to meet the capability requirements of real-time image acquisition systems, such as spaceborne and airborne synthetic aperture radar (SAR) systems. By analysing the principles and models of SAR imaging, this research creatively puts forward the fully parallel processing architecture for the back projection (BP) algorithm based on Field-Programmable Gate Array (FPGA). The processing time consumption has significant advantages compared with existing methods. This article describes the BP imaging algorithm, which stands out with its high processing accuracy and two-dimensional decoupling of distance and azimuth, and analyses the algorithmic flow, operation, and storage requirements. The algorithm is divided into five core operations: range pulse compression, upsampling, oblique distance calculation, data reading, and phase accumulation. The architecture and optimisation of the algorithm are presented, and the optimisation methods are described in detail from the perspective of algorithm flow, fixed-point operation, parallel processing, and distributed storage. Next, the maximum resource utilisation rate of the hardware platform in this study is found to be more than 80%, the system power consumption is 21.073 W, and the processing time efficiency is better than designs with other FPGA, DSP, GPU, and CPU. Finally, the correctness of the processing results is verified using actual data. The experimental results showed that 1.1 s were required to generate an image with a size of 900 × 900 pixels at a 200 MHz clock rate. This technology can solve the multi-mode, multi-resolution, and multi-geometry signal processing problems in an integrated manner, thus laying a foundation for the development of a new, high-performance, SAR system for real-time imaging processing.

Synthetic Aperture Radar (SAR) imagery is widely utilized in military and civilian applications. Recent deep learning advancements have led to improved ship detection algorithms, enhancing accuracy and speed over traditional Constant False-Alarm Rate (CFAR) methods. However, challenges remain with complex backgrounds and multi-scale ship targets amidst significant interference. This paper introduces a novel method that features a context-based decoupled head, leveraging positioning and semantic information, and incorporates shuffle attention to enhance feature map interpretation. Additionally, we propose a new loss function with a dynamic non-monotonic focus mechanism to tackle these issues. Experimental results on the HRSID and SAR-Ship-Dataset demonstrate that our approach significantly improves detection performance over the original YOLOv5 algorithm and other existing methods.

Real-time synthetic aperture radar (SAR) image-processing systems on airborne or spaceborne platforms have constraints in terms of their power consumption, volume, and weight. In order to meet the requirements of these platforms and increase the flexibility of system application, this paper presents a SAR real-time imaging technology based on field-programmable gate array (FPGA) dynamic-reconfiguration technology. First, this technology is used to optimize the algorithm. The entire process flow is then classified into dynamic and static parts. The dynamic part implements numerical calculations, and the static part involves process control, data storage, and peripheral interface. Then, based on dynamic reconfiguration, the processing system is designed, including data interface, data storage, process control, and data operation. Finally, using flight data based on an unmanned aerial vehicle, the performance of the system is verified. The results indicate that the system needs to be run at a 200 MHz frequency for 85.9 s to process data with a size of $65536 \times 65536$ . The system uses approximately 31.4% less resources and consumes 20% less power compared to the traditional method. These experimental results prove the effectiveness of the technology, laying the foundation for the design of high-performance real-time image-processing systems on airborne or spaceborne platforms.

Recently, synthetic aperture radar (SAR) target detection algorithms based on Convolutional Neural Networks (CNN) have received increasing attention. However, the large amount of computation required burdens the real-time detection of SAR ship targets on resource-limited and power-constrained satellite-based platforms. In this paper, we propose a hardware-aware model speed-up method for single-stage SAR ship targets detection tasks, oriented towards the most widely used hardware for neural network computing—Graphic Processing Unit (GPU). We first analyze the process by which the task of detection is executed on GPUs and propose two strategies according to this process. Firstly, in order to speed up the execution of the model on a GPU, we propose SAR-aware model quantification to allow the original model to be stored and computed in a low-precision format. Next, to ensure the loss of accuracy is negligible after the acceleration and compression process, precision-aware scheduling is used to filter out layers that are not suitable for quantification and store and execute them in a high-precision mode. Trained on the dataset HRSID, the effectiveness of this model speed-up algorithm was demonstrated by compressing four different sizes of models (yolov5n, yolov5s, yolov5m, yolov5l). The experimental results show that the detection speeds of yolov5n, yolov5s, yolov5m, and yolov5l can reach 234.7785 fps, 212.8341 fps, 165.6523 fps, and 139.8758 fps on the NVIDIA AGX Xavier development board with negligible loss of accuracy, which is 1.230 times, 1.469 times, 1.955 times, and 2.448 times faster than the original before the use of this method, respectively.

In the traditional processing methods of azimuth multi-channel spaceborne synthetic aperture radar (SAR), the azimuth spectrum reconstruction and subsequent azimuth focusing are always via full-aperture processing. However, if the multi-channel full-aperture echo data are stored on the satellite, and then the full-aperture algorithms are used for the on-board imaging processing, the huge amount of echo data will require more on-board storage resources and computing resources, and the imaging processing time will become longer. To solve above problems, a novel on-board imaging processing algorithm via the idea that the data acquisition and the on-board imaging processing of the sub-aperture data are carried out simultaneously is proposed in this paper. In the algorithm, the azimuth spectrum ambiguity is eliminated by the sub-aperture azimuth spectrum reconstruction. Then, the range cell migration correction (RCMC) and the range compression for the unambiguous sub-aperture signals are accomplished by the chirp scaling algorithm (CSA). After that, the low-resolution subaperture images are got via the sub-aperture focusing. By coherently combining all sub-aperture images, the final result with high-resolution of all echo data can be obtained. At last, the simulation for the point targets is given to verify the effectiveness of the proposed algorithm.

The deep learning object detection algorithm has been widely applied in the field of synthetic aperture radar (SAR). By utilizing deep convolutional neural networks (CNNs) and other techniques, these algorithms can effectively identify and locate targets in SAR images, thereby improving the accuracy and efficiency of detection. In recent years, achieving real-time monitoring of regions has become a pressing need, leading to the direct completion of real-time SAR image target detection on airborne or satellite-borne real-time processing platforms. However, current GPU-based real-time processing platforms struggle to meet the power consumption requirements of airborne or satellite applications. To address this issue, a low-power, low-latency deep learning SAR object detection algorithm accelerator was designed in this study to enable real-time target detection on airborne and satellite SAR platforms. This accelerator proposes a Process Engine (PE) suitable for multidimensional convolution parallel computing, making full use of Field-Programmable Gate Array (FPGA) computing resources to reduce convolution computing time. Furthermore, a unique memory arrangement design based on this PE aims to enhance memory read/write efficiency while applying dataflow patterns suitable for FPGA computing to the accelerator to reduce computation latency. Our experimental results demonstrate that deploying the SAR object detection algorithm based on Yolov5s on this accelerator design, mounted on a Virtex 7 690t chip, consumes only 7 watts of dynamic power, achieving the capability to detect 52.19 512 × 512-sized SAR images per second.