This letter presents a broadband multistage low-noise amplifier (LNA) in a 0.15- $\mu $ m GaAs pseudomorphic high-electron-mobility (pHEMT) process. The LNA employs multiple bandwidth extension techniques, including cascode, feedback, and gain-enhanced source–drain coupled line (SDCL). The SDCL enhances the gain by combining the source and drain signals and compensates the gain roll-off of the amplifier, which is first proposed in this letter to our knowledge. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA, achieving a wide bandwidth with high gain. The measured results show that the LNA obtains an average gain of 24.7 dB and a noise figure (NF) of 1.7–2.8 dB in 0.5–24 GHz, with a compact chip area of only 1.47 mm $^{2}$ .

Recently, deep learning has greatly promoted the development of detection methods for ship targets in synthetic aperture radar (SAR) images. However, existing detection networks are mostly based on large-scale models and high-cost computations, which require high-performance computing equipment to realize real-time processing and limit their hardware transplantation to onboard platforms. To address this problem, a lightweight ship detection network via YOLOX-s is proposed in this paper. Firstly, we remove the computationally heavy pyramidal structure and build a streamlined network based on a one-level feature for higher detection efficiency. Secondly, to expand the limited receptive field and enhance the semantic information of a single-feature map, a residual asymmetric dilated convolution (RADC) block is proposed. Through four branches with different dilation rates, the RADC block can help the detector to capture various ships in complex backgrounds. Finally, to tackle the imbalance problem between ships of different scales in the training stage, we put forward a balanced label assignment strategy called center-based uniform matching. To verify the effectiveness of the proposed method, we conduct extensive experiments on the SAR Ship Detection Dataset (SSDD) and High-Resolution SAR Images Dataset (HRSID). The results show that our method can achieve comparable performance to general detection networks with much less computational cost.

This study conducts an in-depth evaluation of imaging algorithms and software and hardware architectures to meet the capability requirements of real-time image acquisition systems, such as spaceborne and airborne synthetic aperture radar (SAR) systems. By analysing the principles and models of SAR imaging, this research creatively puts forward the fully parallel processing architecture for the back projection (BP) algorithm based on Field-Programmable Gate Array (FPGA). The processing time consumption has significant advantages compared with existing methods. This article describes the BP imaging algorithm, which stands out with its high processing accuracy and two-dimensional decoupling of distance and azimuth, and analyses the algorithmic flow, operation, and storage requirements. The algorithm is divided into five core operations: range pulse compression, upsampling, oblique distance calculation, data reading, and phase accumulation. The architecture and optimisation of the algorithm are presented, and the optimisation methods are described in detail from the perspective of algorithm flow, fixed-point operation, parallel processing, and distributed storage. Next, the maximum resource utilisation rate of the hardware platform in this study is found to be more than 80%, the system power consumption is 21.073 W, and the processing time efficiency is better than designs with other FPGA, DSP, GPU, and CPU. Finally, the correctness of the processing results is verified using actual data. The experimental results showed that 1.1 s were required to generate an image with a size of 900 × 900 pixels at a 200 MHz clock rate. This technology can solve the multi-mode, multi-resolution, and multi-geometry signal processing problems in an integrated manner, thus laying a foundation for the development of a new, high-performance, SAR system for real-time imaging processing.

This paper analyzes the main factors limiting the bandwidth expansion of low-noise amplifiers (LNA) and designs a broadband LNA with a bandwidth of 2-40.5 GHz. The LNA is designed using multiple bandwidth expansion methods, including cascode, resistance feedback, and cascode Darlington amplifier. The amplitude-frequency characteristics and bandwidth expansion principle of the three structures are studied theoretically based on the small-signal equivalent circuit model. Thanks to these techniques, a three-stage LNA is designed in a 0.15-μm GaAs pseudomorphic high-electron-mobility (pHEMT) process. The measured results show that the designed LNA achieves an average gain of 21.6 dB in 2-40.5 GHz while maintaining a noise figure (NF) below 3.6 dB. The measured output 1-dB gain compression point (OP1 dB) is from 4.5 to 12.8 dBm and the input/output return loss are better than 5 dB. The chip area is only 1.57 mm ² , including input and output test pads.

In millimeter wave (MMW) and terahertz (THz) band, the operation frequency is high and there are challenges in fabrication and micro-assembly processes, bringing high-accuracy requirements and high manufacture cost. In this paper, high-gain substrate integrated antennas with low fabrication cost are presented for MMW/THz applications. The basic antenna consists of two parallel TE201 resonant cavities and is directly fed by a grounded coplanar waveguide (GCPW). Radiation slot apertures are modified to increase aperture radiation efficiency and improve radiation patterns and gain. The antenna scheme is analyzed and a 220 GHz 2×2 slot array antenna is developed as an example. To further improve the antenna gain with low fabrication cost and low feeding network loss, the basic antenna is explored to feed a modified dielectric plate lens. The high-gain scheme and design flow chart are provided. Both basic and improved structures are fabricated by normal single layer printed circuit board (PCB) technology and high antenna gains are achieved. The measured peak gain of the basic antenna and the antenna with dielectric plate lens are 13.5 dBi and 20.2 dBi respectively. The measured return losses are better than 10 dB from 192 GHz to 247 GHz. The antennas have advantages of simple antenna feeding structure, low fabrication cost, wide bandwidth, and high gain.

A multiple feedback-based technique is presented to improve broadband simultaneous noise and impedance matching (BSNIM) performance in a GaAs low-noise amplifier (LNA). It consists of dual reactive feedback for the first stage and frequencydependent feedback loops (FDFLs) for the succeeding stages. Compared to existing BSNIM technologies, the proposed method completes the theoretical derivation of the required load and can provide flexible solutions, which effectively increases the optimization opportunity. Besides, in order to achieve the required load, a structure composed of low-Q high order LC-ladder networks and FDFLs are introduced, which greatly reduce the difficulty of impedance conversion. The detailed strategies for BSNIM are also given. To verify feasibility, a 6-14 GHz three-stage common-source LNA has been fabricated via 0.15-μm GaAs pHEMT process, with a measured gain of 26.8 ± 0.75 dB, a minimum noise of 1.21 dB, and S11 of less than -15 dB throughout the entire operating band.