With the increasing interconnectivity of devices, the Internet of Things (IoT) has revolutionized the industry and daily life. However, the proliferation of IoT devices has also increased security risks, necessitating robust protection mechanisms for sensitive data and critical infrastructure. The Advanced Encryption Standard (AES) remains the benchmark for securing IoT systems while balancing low power consumption, minimal area usage, and moderate throughput with high security. This paper offers a comprehensive review of the latest lightweight AES architectural designs, including optimizations to the Substitution Box (S-Box), Sub-Bytes, Shift Rows, Mix Columns, and Add Round Key steps, assessing their impact on gate count, area, maximum frequency, power consumption, and throughput in field programable gate arrays (FPGA) and Application-specific integrated circuit (ASIC) implementations. In addition, this study addresses vulnerabilities in lightweight AES cryptographic hardware to side-channel attacks (SCA), specifically focusing on Differential Fault Analysis (DFA). Furthermore, the analysis explored fault scenarios, rounds, and injection positions to evaluate fault severity. Countermeasures to DFA are reviewed, emphasizing fault detection methods, error detection levels, protection positions, and associated design overheads such as area, frequency, and throughput penalties, with special consideration for resource-constrained IoT devices. This study identifies critical gaps in lightweight AES and security challenges while discussing countermeasures that balance security with design efficiency. Finally, this study provides valuable insights for finding research directions to strengthen the robustness of AES in lightweight IoT environments.

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation.

The simulation of massive multiple-input multiple-output (MIMO) channel models is becoming increasingly important for testing and validation of fifth-generation new radio (5G NR) wireless networks and beyond. However, simulation performance tends to be limited when modeling a large number of antenna elements combined with a complex and realistic representation of propagation conditions. In this paper, we propose an efficient implementation of a 3rd Generation Partnership Project (3GPP) three-dimensional (3D) channel model, specifically designed for graphics processing unit (GPU) platforms, with the goal of minimizing the computational time required for channel simulation. The channel model is highly parameterized to encompass a wide range of configurations required for real-world optimized 5G NR network deployments. We use several compute unified device architecture (CUDA)-based optimization techniques to exploit the parallelism and memory hierarchy of the GPU. Experimental data show that the developed system achieves an overall speedup of about 240× compared to the original C++ model executed on an Intel processor. Compared to a design previously accelerated on a datacenter-class field programmable gate array (FPGA), the GPU design has a 33.3% higher single-precision performance but a 7.5% higher power consumption. The proposed GPU accelerator can provide fast and accurate channel simulations for 5G NR network planning and optimization.