Dejun Wang

Prof. Dr. Dejun Wang

Dalian University of Technology, Dalian, Liaoning, China

Research Focus & Metrics

Academic Career Length

16Years (2011-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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25 June 2012 in Applied Physics Letters
Verified
Journal Article
Closed access
LHLingqin Huang
Lingqin Huang
BLBingbing Liu
Bingbing Liu
QZQiaozhi Zhu
Qiaozhi Zhu
SCSuhua Chen
Suhua Chen
MGMingchao Gao
Mingchao Gao
DWDejun Wang
Dejun Wang
Ti Ohmic contacts to relatively highly doped (1 × 1018 cm−3) n-type 4H-SiC have been produced, without high temperature annealing, by means of low temperature electronic cyclotron resonance microwave hydrogen plasma pre-treatment (HPT) of the SiC surface. The as-deposited Ti/4H-SiC contacts show Ohmic properties, and the specific contact resistance obtained is as low as 2.07 × 10−4 Ω·cm2 after annealing at low temperatures (400 °C). This is achieved by low barrier height at Ti/SiC interface, which could be attributed to decrease of surface states density by the HPT releasing Fermi level pinning, and to band-gap narrowing, image-force, and thermionic-field emission at high doping.

20 January 2021 in Journal of Physics D: Applied Physics
Verified
Journal Article
Closed access
PDF file
CYChao Yang
Chao Yang
SWShengsheng Wei
Shengsheng Wei
DWDejun Wang
Dejun Wang
Although silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are commercially available, bias temperature instability (BTI) defined as shifts in V th in SiC MOSFET and V fb in MOS capacitor after the device is operated at a high temperature, seriously affects device reliability and limits further commercial applications. These instabilities are mainly attributed to charge trapping at and near the SiC/SiO 2 interface and mobile ions in a gate oxide. The consequences of V th instability are serious and can worsen the performance and lifetime of SiC MOS devices. In this review, the SiC/SiO 2 interface issue is introduced, and BTI occurring in current SiC MOS devices is described in detail. V th / V fb instability behavior induced by measurement and stress conditions, microscopic defects and instability mechanisms, recent measurement techniques of near-interfacial oxide traps, and BTI improvement resulting from the fabrication processes are described. BTI improvement mainly involves the control of charge trapping and movements of ions. The fabrication processes are related to oxidation and pre- and post-oxidation treatments. This review can help deepen our understanding of BTI and reduce its influence on SiC MOS devices performance.

29 June 2022 in Applied Surface Science
Verified
Journal Article
Closed access
JBJiao Bai
Jiao Bai
WXWeiwei Xie
Weiwei Xie
WZWeiqi Zhang
Weiqi Zhang
ZYZhipeng Yin
Zhipeng Yin
SWShengsheng Wei
Shengsheng Wei
DWDejun Wang
Dejun Wang

22 August 2011 in Applied Physics Letters
Verified
Journal Article
Closed access
QZQiaozhi Zhu
Qiaozhi Zhu
LHLingqin Huang
Lingqin Huang
WLWenbo Li
Wenbo Li
SLShenmin Li
Shenmin Li
DWDejun Wang
Dejun Wang
The chemical structure of SiO2/4H-SiC (0001) interface transition region is investigated using angle-dependent x-ray photoelectron spectroscopy. The relative intensities of various silicon oxycarbides (SiOxCy) components as a function of polar emission angle suggest that SiOC3, SiO2C2, SiO3C, and SiO2 have different depth distributions at the interface. Then a nonabrupt four-layer structure model is proposed. And the relative intensities of various SiOxCy species are fitted based on the model by an electron damping scheme. The well fitted results indicate that the SiO2/4H-SiC (0001) interface transition region can be described by a chemically nonabrupt four-layer structure model well.

27 October 2015 in Sensors
Verified
Journal Article
Open access
PDF file
HHHaiyun Huang
Haiyun Huang
DWDejun Wang
Dejun Wang
YXYue Xu
Yue Xu
This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

29 March 2023 in ACS Applied Materials & Interfaces
Verified
Journal Article
Closed access
SWShengsheng Wei
Shengsheng Wei
JBJiao Bai
Jiao Bai
WXWeiwei Xie
Weiwei Xie
YSYan Su
Yan Su
FQFuwen Qin
Fuwen Qin
DWDejun Wang
Dejun Wang