This article presents a switched-transformer-based polar Doherty digital power amplifier (DPA) for deep back-off efficiency enhancement. A single-transformer-footprint parallel-combining transformer (PCT) power combiner is introduced for 1.3-3.5-GHz wide frequency coverage, dynamic load modulation at 0-/6-/12-/18-dB power back-off (PBO) levels, and an ultra-compact die size. Implemented in 40-nm CMOS, the DPA is powered by a 1.1-V supply and only occupies 0.7 x 1.15 mm² chip area. It achieves 21.4-dBm peak power with the power added efficiencies (PAEs) of 31.3%, 27.7%, 16.6%, and 7.7% for 0-/6-/12-/18-dB PBOs at 1.5 GHz. With 20-MHz 64QAM long term evolution (LTE) signal, the DPA achieves Pavg of 15.2 dBm and the average PAE of 25.3% with -32.5-dB error vector magnitude (EVM) at 1.5 GHz. Moreover, for 20-MHz 64 QAM WLAN signal, Pavg of 14.7 dBm with the average PAE of 20.1% is obtained with - 25-dB EVM at 2.4 GHz.

Gesture air-writing is an advanced nontouching interaction method that replaces traditional typewriter keyboards, touch screens and other input devices. Due to its low power consumption, noncontact detection and independence from light conditions, millimeter wave radar has become a valuable gesture air-writing solution. In this paper, we proposed a prototype of a gesture air-writing tracking system that is based on the 24-GHz frequency-modulated continuous-wave (FMCW) radar system-on-chip (SoC). The transmitted chirp signal of this radar chip covers up to a 4-GHz bandwidth, which provides sufficient range resolution to track hand gestures. With the development of single input, multiple output (SIMO) antennas, the air-writing symbols can be reconstructed in an observation plane. A system design and signal processing algorithm for gesture air-writing applications is proposed for the prototype system in this paper. To test the performance of the proposed method, experiments with cases of five simple gestures, air-writing numbers and letter tracking are carried out. The experimental results verify the efficiency and accuracy of the proposed method.

This article presents a 15-bit quadrature digital power amplifier (DPA) with in-phase and quadrature (IQ)-cell-sharing and transformer-based Doherty operation, which compensates the 3-dB power loss in traditional quadrature architecture and enhances efficiency. Efficiency enhancement at 3-/6-dB power backoffs (PBOs) is obtained on the IQ complex plane to improve average efficiency. A single-transformer-footprint parallel-combining transformer (PCT) power combiner is implemented for compact die size. Fabricated in a 55-nm CMOS technology, the DPA is powered by 1.2-/2.4-V supply voltages and the core circuit only occupies 1.05 $\times $ 1.14-mm ² chip area. It achieves 29.3-dBm peak output power with power added efficiency (PAE) of 43.1%. With 10-MHz 64-quadratic-amplitude modulation (QAM) local thermal equilibrium (LTE) signal, the DPA achieves $P_{\mathrm {avg}}$ of 23.62 dBm and the average PAE of 24.4% with −25.6-dB error vector magnitude (EVM) at 0.85 GHz without using any digital predistortion (DPD) technique. Moreover, for 20-MHz 64-QAM wireless local area network (WLAN) signal, $P_{\mathrm {avg}}$ of 21.01 dBm and the average PAE of 20.1% are obtained with −25.1-dB EVM.

In this paper, a single-beam-scanning metasurface with dual circular polarization using hybrid coding mechanism is presented, which can steer the scattered wave in a large range of angles under the planar incident wave. In order to suppress the grating lobes generated by periodic 1-bit phase quantization errors, elaborately designed two-dimensional fixed phase delays (FPDs) are introduced. The 1-bit active coding is designed based on the current reversal method, which realizes two states with 180° phase difference over the frequency range of 8.5 GHz - 11 GHz by switching two PIN diodes for both left-handed circular polarization (LHCP) and right-handed circular polarization (RHCP) incidence. The passive coding is realized by rotating the metasurface unit cell based on Pancharatnam-Berry (P-B) phase principle to introduce the two-dimensional FPD. The proposed design mechanism is theoretically analyzed, full-wave simulated, and demonstrated by experiment. An 8×8 metasurface prototype is fabricated and measured. The experimental results show that steered beams from -30° to +30° without grating lobes in both x-o-z plane and y-o-z plane can be obtained around 9.5 GHz. The side lobe level (SLL) can be minimized to -8.87 dB, and the beam pointing deviation is within 3°.

This article presents a wideband, low-jitter frequency synthesizer utilizing a dual-mode voltage-controlled oscillator (VCO). Mode imbalance in the dual-mode VCO is analyzed theoretically and compensated through the proposed symmetric figure-8 transformer and capacitor arrays. The compact mode-switching circuitry fundamentally eliminates mode ambiguity in multi-mode autonomous circuits. A computer-aided algorithm based on sequential least-squares programming (SLSQP) and hierarchical optimization method is developed to automatically optimize the capacitor array in the wideband VCO. The implemented dual-mode VCO suppresses the phase noise (PN) difference across the operating frequency range, which further enables a sub-sampling phase-locked loop (SSPLL) to achieve near-minimum jitter across a wide frequency range without loop gain adaptation. Fabricated in a 40-nm CMOS process, the wideband SSPLL covers the frequency range of 7.9–14.3 GHz with 14.1–17.2-mW power consumption and occupies only 0.18-mm $^2$ area. The SSPLL achieves better than $-$ 115-dBc/Hz in-band PN at a 10-GHz carrier. The rms jitter is less than 85 fs across the whole frequency range. The corresponding figure-of-merit tuning (FoM $_T$ ) is $-$ 247.1 to $-$ 248.1 dB.

This brief presents a wake-up mechanism for orthogonal frequency division multiplexing (OFDM) modulation-based systems by coding a low data-rate wake-up signal in transmitter without extra circuitry overhead. It is achieved by controlling data pattern for each OFDM subcarrier in one symbol of frame to produce an equivalent amplitude-modulated (AM) signal as a wake-up query without contaminating protocol integrity. A low-power wake-up receiver is used to demodulate this signal and interpret the wake-up query. A system using proposed wake-up mechanism has been built based on IEEE 802.11ah standard. Measurement results demonstrate that an AM-type wake-up signal with a data-rate of 31.25 Kb/s is generated through the proposed method. Moreover, an envelope detector with -35-dBm sensitivity at 900 MHz has been implemented in 0.13-μm CMOS technology for wake-up signal detection and consumes 120-nW power.