This article presents a 13.56-MHz wireless power and data transfer receiver for implantable biomedical devices. To avoid the efficiency reduction of energy harvesting caused by the large amplitude modulation (AM) modulation depth (MD), and maintain low-power consumption for data receiving, an envelope-detector-based receiver with shifted limiters is designed for signal demodulation. The detectable MD is as low as 0.1%. Moreover, a dynamic impedance matching controller is proposed to adjust the input impedance of the rectifier automatically and thus optimize the power conversion efficiency (PCE). By using these techniques, when keeping the bit error rate (BER) of the proposed receiver to 10 ^-3 for 100-kb/s data rate in the wireless amplitude shift keying (ASK) data receiver, the effective PCE of the corresponding wireless power receiver can be up to 75.4%.

This article presents a switched-transformer-based polar Doherty digital power amplifier (DPA) for deep back-off efficiency enhancement. A single-transformer-footprint parallel-combining transformer (PCT) power combiner is introduced for 1.3-3.5-GHz wide frequency coverage, dynamic load modulation at 0-/6-/12-/18-dB power back-off (PBO) levels, and an ultra-compact die size. Implemented in 40-nm CMOS, the DPA is powered by a 1.1-V supply and only occupies 0.7 x 1.15 mm² chip area. It achieves 21.4-dBm peak power with the power added efficiencies (PAEs) of 31.3%, 27.7%, 16.6%, and 7.7% for 0-/6-/12-/18-dB PBOs at 1.5 GHz. With 20-MHz 64QAM long term evolution (LTE) signal, the DPA achieves Pavg of 15.2 dBm and the average PAE of 25.3% with -32.5-dB error vector magnitude (EVM) at 1.5 GHz. Moreover, for 20-MHz 64 QAM WLAN signal, Pavg of 14.7 dBm with the average PAE of 20.1% is obtained with - 25-dB EVM at 2.4 GHz.

This paper presents a dual-band high-power digital polar Doherty power amplifier (PA). A current-mode parallel-combining transformer (PCT) power combiner is introduced for Doherty operation, which realizes simultaneous dual-band coverage, high output power, and backoff efficiency enhancement with an ultra-compact single-transformer footprint. The PA is implemented in 55-nm CMOS and occupies 1.11 mm² die area. It achieves 28.9-dBm peak Pout with 36.8% PAE in low band (LB) and 27.0-dBm peak Pout with 25.4% PAE in high band (HB). For 12-subcarrier 180-kHz bandwidth cellular narrowband Internet-of-Things (NB-IoT) signals, the peak Pavg of 24.4 dBm with average PAE of 29.5% at 850 MHz and the peak Pavg of 23.0 dBm with average PAE of 17.9% at 1.7 GHz are obtained with -21.6-dB error vector magnitude (EVM). Moreover, the PA achieves 20.8-dBm Pavg, 22.7% average PAE, and -30.5-dB EVM for 20-MHz 256-QAM WLAN signal.

This article presents a wideband, low-jitter frequency synthesizer utilizing a dual-mode voltage-controlled oscillator (VCO). Mode imbalance in the dual-mode VCO is analyzed theoretically and compensated through the proposed symmetric figure-8 transformer and capacitor arrays. The compact mode-switching circuitry fundamentally eliminates mode ambiguity in multi-mode autonomous circuits. A computer-aided algorithm based on sequential least-squares programming (SLSQP) and hierarchical optimization method is developed to automatically optimize the capacitor array in the wideband VCO. The implemented dual-mode VCO suppresses the phase noise (PN) difference across the operating frequency range, which further enables a sub-sampling phase-locked loop (SSPLL) to achieve near-minimum jitter across a wide frequency range without loop gain adaptation. Fabricated in a 40-nm CMOS process, the wideband SSPLL covers the frequency range of 7.9–14.3 GHz with 14.1–17.2-mW power consumption and occupies only 0.18-mm $^2$ area. The SSPLL achieves better than $-$ 115-dBc/Hz in-band PN at a 10-GHz carrier. The rms jitter is less than 85 fs across the whole frequency range. The corresponding figure-of-merit tuning (FoM $_T$ ) is $-$ 247.1 to $-$ 248.1 dB.

A novel type of highly efficient conditional feedthrough pulse-triggered flip-flop (P-FF) is proposed and demonstrated. The data-to-output (D-to-Q) delay in this circuit was highly optimized using predischarging and conditional signal feedthrough schemes. Power consumption was also reduced using a shared pulse generator and an output feedback-controlled conditional keeper, which diminished the floating status of the internal node. The driving strength of this design was further enhanced by including an additional pull-down path at the output node. Various postlayout simulation results applied to 16-nm FinFET technology demonstrated a higher energy efficiency (at all input data toggle rates) for the proposed topology than comparable P-FF devices. Notably, the proposed model achieved a 62% D-to-Q delay reduction, compared to a transmission gate FF, outperforming the device by more than 66% in terms of power efficiency and 87% in energy efficiency (at a 50% input data toggle rate). Improvements were even more significant in comparison with other conventional P-FFs. These results suggest the proposed design to be a viable new option for high-efficiency sequential elements in high-speed applications.

Ultra-high frequency (UHF) radio frequency identification (RFID) system suffers from large leakage of the carrier due to insufficient TX-to-RX isolation. A narrowband leaking carrier canceller (LCC) for UHF RFID is proposed to enhance the isolation. Hardware realization is carried out based on simulation model in ADS (advanced design system). Measurement results indicate that the TX-to-RX isolation is improved from 20 dB to above 40 dB within UHF RFID frequency band of 920-925 MHz. Upper limit of increase in isolation versus amplitude and phase distortion are also presented and discussed.