Electron trap generation in thermally grown silicon dioxide (SiO₂) during Fowler–Nordheim (FN) stress is investigated by using an aluminium‐gated capacitor structure. The generated electron traps are characterized by the avalanche electron injection technique. The experimental results support the model that electron trapping in oxide follows the first‐order kinetics and may have multiple‐capture cross sections. It is found that both donorlike (positive charge related) and acceptorlike (neutral before capturing electron) traps are generated and they behave differently. The donorlike trap is not stable at or above room temperature and its effective density saturates as the stressing time increases, while the opposite is true for the acceptorlike trap. The electron‐capture cross section of donorlike trap spreads from 10⁻¹⁸ to over 10⁻¹⁴ cm², but the capture cross section of the generated acceptorlike trap is limited in the range of (4.5–9)× 10⁻¹⁷ cm². The acceptorlike trap is generated by the interaction between free holes and SiO₂ and hole trapping leads to donorlike traps. The relation between the generated trap and the as‐grown trap will be discussed. Comparison of the electron traps generated by FN stress with those by irradiation and hot hole injection indicates that the electron trap generation under these different stressing conditions is controlled by the same mechanism. The necessary condition for electron trap generation is the presence of holes in the oxide, rather than a high electrical field.

Predicting negative bias temperature instability (NBTI) lifetime can be dangerous since it is difficult to assess its safety margin. The common technique uses gate bias V_g acceleration to reduce the test time, and the data were typically obtained from quasi-DC measurements. Recently, it has been shown that substantial recovery occurs during the quasi-DC measurement, and the suppression of recovery requires using ultrafast pulse measurement, where time was reduced to the order of microseconds. In a real circuit, different transistors have different levels of recovery, and the worst case scenario is when recovery is suppressed. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional V_g acceleration technique can still be used. This work will show that the prediction based on the V_g acceleration results in a substantial error, and its cause will be analyzed. To predict the worst case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects, and it no longer follows a simple power law. Based on the new kinetics, a single-test prediction method is proposed, and its safety margin is estimated to be 50%.

Positive charges (PCs) in gate dielectric shift the threshold voltage and cause a time-dependent device variability. To assess their impact on circuits, it is useful to know their distribution for a wide energy range both within and beyond silicon bandgap. Such a distribution is still missing, and a technique for its extraction has not been demonstrated yet. The central objective of this paper is, for the first time, to develop a new fast technique and to demonstrate its capability for probing the energy distribution of PCs over such a wide energy range. Results show that PCs can vary significantly with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps that are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence-band edge are from created defects. The PCs within the bandgap have a peak near Ev + 0.8 eV and saturate for either longer stress time or higher stress temperature. In contrast, the PCs above a conduction band edge, namely the antineutralization positive charges, do not saturate, and their generation is clearly thermally accelerated.

Resistive switching memory devices can be categorized into either filamentary or non-filamentary ones depending on the switching mechanisms. Both types have been investigated as novel synaptic devices in hardware neural networks, but there is a lack of comparative study between them, especially in random telegraph noise (RTN) which could induce large resistance fluctuations. In this letter, we analyze the amplitude and occurrence rate of RTN in both Ta ₂ O ₅ filamentary and TiO ₂ /a-Si (a-VMCO) non-filamentary resistive switching memory (RRAM) devices and evaluate its impact on the pattern recognition accuracy of neural networks. It is revealed that the non-filamentary RRAM has a tighter RTN amplitude distribution and much lower RTN occurrence rate than its filamentary counterpart, which leads to negligible RTN impact on recognition accuracy, making it a promising candidate in synaptic application.