In this paper, a high-quality sputtered-GeSn layer on Ge (100) with a Sn composition up to 7% was demonstrated. The crystallinity of the GeSn layer was investigated via high-resolution X-ray diffraction (HR-XRD) and the strain relaxation degree of the GeSn layer was evaluated to be approximately 50%. A novel method was also proposed to evaluate the averaged threading dislocation densities (TDDs) in the GeSn layer, which was obtained from the rocking curve of GeSn layer along the (004) plane. The photoluminescence (PL) measurement result shows the significant optical emission (1870 nm) from the deposited high-quality GeSn layer. To verify whether our deposited GeSn can be used for optoelectronic devices, we fabricated the simple vertical p-i-n diode, and the room temperature current–voltage (I–V) characteristic was obtained. Our work paves the way for future sputtered-GeSn optimization, which is critical for optoelectronic applications.

Electroplating has become a cornerstone technology in semiconductor manufacturing, enabling high-performance interconnects and advanced packaging. Since the introduction of the Damascene Cu process at the 180 nm node, it has evolved to meet the demands for precision, uniformity, and scalability in miniaturized nodes and complex packaging architectures. The shift to horizontal electroplating systems has enhanced uniformity and process stability, particularly for applications such as TSVs, Cu pillars, micro-bumps, and RDLs. Emerging innovations like pulse electroplating, segmented anode control, and AI-driven monitoring are addressing the challenges of fine-pitch interconnects and emerging interconnect materials, such as cobalt. These advancements are critical for high-density interconnects used in AI, HPC, and high-frequency applications. This review explores the advancements in electroplating technologies, focusing on their role in semiconductor manufacturing. It highlights the evolving equipment designs and their implications for achieving precision, scalability, and reliability at advanced nodes. The ongoing development of electroplating equipment and techniques will support the reliability and performance of future semiconductor devices, reinforcing electroplating as a cornerstone technology in advanced packaging and fabrication.

A visual and tactile multisensory integrated system is essential for human walking due to the demand for real-time interactions between perception and action. Here, a piezoresistor and MoS₂ field effect transistor are combined to construct an artificial integration nervous system to simulate perception and synaptic plasticity. The key characteristics of synaptic plasticity are successfully demonstrated by individual pressure signals, individual optical signals, and the synergy of optical and pressure signals, which are based on the electron trapping-detrapping mechanism at the MoS₂/SiO₂ interface. We demonstrate that perception under synergy is stronger than perception under optical or pressure signal alone, which is similar to a biological system. Moreover, various distinguishable motion scenarios (combination of the following conditions: external lighting environment of day or night, flat or rough road, and movement state of walking or running) are simulated and verified by adjusting the amplitude and frequency of the optical and pressure signals.

The properties of photodetectors based on two-dimensional materials can be significantly enhanced by avalanche effect. However, a high avalanche breakdown voltage is needed to reach impact ionization, which leads to high power consumption. Here, we report the unique features of a low-voltage avalanche phototransistor formed by an in-plane WSe₂ field effect transistor (FET) with an out-of-plane WSe₂/WS₂ P—N heterojunction (HJ FET). The avalanche breakdown voltage in the device can be decreased from −31 to −8.5 V when compared with that in WSe₂ FET. The inherent mechanism is mainly related to the redistributed electric field in the WSe₂ channel after the formation of the out-of-plane P—N heterojunction. When the bias voltage is −16.5 V, the photoresponsivity in the HJ FET is enhanced from 1.5 to 135 A/W, which is significantly higher than that in the WSe₂ FET because of the obvious reduction of the avalanche breakdown voltage. Moreover, HJ FET shows a higher responsivity than WSe₂ FET in the range of 400–1,100 nm under low bias voltage. This phenomenon is caused by accelerating electron—hole spatial separation in the heterojunction. These results indicate that the use of an WSe₂ FET with an out-of-plane WSe₂/WS₂ heterojunction is ideal for high-performance photodetectors with low power consumption.