In this paper, a high-quality sputtered-GeSn layer on Ge (100) with a Sn composition up to 7% was demonstrated. The crystallinity of the GeSn layer was investigated via high-resolution X-ray diffraction (HR-XRD) and the strain relaxation degree of the GeSn layer was evaluated to be approximately 50%. A novel method was also proposed to evaluate the averaged threading dislocation densities (TDDs) in the GeSn layer, which was obtained from the rocking curve of GeSn layer along the (004) plane. The photoluminescence (PL) measurement result shows the significant optical emission (1870 nm) from the deposited high-quality GeSn layer. To verify whether our deposited GeSn can be used for optoelectronic devices, we fabricated the simple vertical p-i-n diode, and the room temperature current–voltage (I–V) characteristic was obtained. Our work paves the way for future sputtered-GeSn optimization, which is critical for optoelectronic applications.

This paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 MΩ at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 μVrms over the 0.5–1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 × 0.47 mm² on the chip, with a power consumption of 8.96 μW.

The reliability of nanoscale electronic systems is important in various applications. However, they are becoming increasingly vulnerable to atmospheric neutrons. This research conducted spallation neutron irradiations on a Xilinx Zynq-7000 system on a chip using the China Spallation Neutron Source. The results were analyzed in combination with a Monte Carlo simulation to explore the impact of atmospheric neutrons on the single event effects of the target system on chip. Meanwhile, the contribution of thermal neutrons to the chip’s single event effect susceptibility was also assessed. It was found that absorbing thermal neutrons with a 2 mm Cd sheet can protect against the single event effect on the system on the chip by about 44.4%. The effects of B and Hf elements, inside the device, on a single event effect of the Xilinx Zynq-7000 system on chip were evaluated too. Additionally, it was discovered that ¹⁰B interacting with thermal neutrons was the primary cause of the thermal neutron-induced single event effect in the system on chip. Although Hf has a high neutron capture cross section, its presence does not significantly affect the sensitivity to single event effects. However, during atmospheric neutron irradiation, the presence of Hf increases the possibility of depositing the total dose in the tested chip.

The conventional high-precision single-slope analog to digital converter (SS ADC) integrated with time-todigital converters (TDCs) requires the introduction of precise delay lines and multiphase high-frequency clocks, leading to increased chip area and power consumption that degrade the performance of highly compact CMOS image sensors (CISs). This article presents a new SS ADC incorporating a level encoding TDC. By replacing clock-edge-based time tracking with logic-level encoding, the TDc’s clock requirement is reduced from $2^{n}$ to n. This innovation mitigates clock jitter effects and lowers power consumption. Moreover, the reduction in the number of clock signals simplifies the layout routing, which is a critical factor for highly compact column-level readout in such CISs. The proposed method performs a 12-bit coarse conversion using the SS ADC and a 2-bit fine conversion using the TDC. The SS ADC is designed in the 55 nm 1P4M CMOS process and implemented in an 8192 (H) × 8192 (V) CIS chip successfully. Simulation and test results show that the conversion time is $10.2~ \mu{\mathrm {s}}$ , power consumption is $73.1~ \mu{\mathrm {W}}$ , differential non-linearity (DNL) is +0.9/.0.8 LSB, integral nonlinearity (INL) is +1.2/.1.5 LSB, and the figure of merit (FoM) is 83.8 fJ/step, demonstrating the potential applications in ultrahigh-resolution, smallfeature- size CISs.

This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally, SEUs are considered to have negative effects on electronic systems or designs, but the current study demonstrates that they can also have positive contributions to the DNN on the MPSoC. The assertion that SEUs can have positive contributions to electronic system design was supported by conducting fault injections through dynamic reconfiguration on DNNs implemented on a 16nm FinFET technology Zynq UltraScale+ MPSoC. The results of the current study were highly significant, indicating that an SEU in configuration memory could result in an impressive 8.72% enhancement in DNN recognition on the MPSoC. One possible cause is that SEU in the configuration memory leads to slight changes in weight or bias values, resulting in improved activation levels of neurons and enhanced final recognition accuracy. This discovery offers a flexible and effective solution for boosting DNN performance on the MPSoC platform.

This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect in the high-temperature range of 300 K to 450 K. The physical mechanism underlying the triggering of SEL in CMOS devices at high temperatures is revealed. The results show that when the linear energy transfer (LET) value is 75 MeV cm²/mg, the CMOS devices do not exhibit SEL effects at 300 K and 350 K. However, when the temperature rises to 400 K, a significant latch-up effect occurs, which becomes more pronounced with increasing temperature. Additionally, at a supply voltage of 1.2 V and a temperature of 450 K, the LET threshold for triggering SEL in CMOS devices decreases by 91.4% compared to 75 MeV cm²/mg at 300 K, dropping to 6 MeV cm²/mg. As the temperature increases, the latch-up trigger current of the CMOS devices decreases from 1.18 × 10⁻⁴ A/μm at 300 K to 4.65 × 10⁻⁵ A/μm at 450 K, and the hold voltage decreases from 1.48 V at 300 K to 1.07 V at 450 K.