Tunnel FET (TFET) has potential applications in the next generation ultra-low power transistor to substitute the conventional FETs. It can offer very steep inverse subthreshold swing slope to maintain a low leakage current, thus it can be very essential for limiting power consumption in MOSFETs. The carriers in TFET transport from source to channel by the band-to-band tunneling (BTBT) mechanisms. To realize high saturation currents of TFET, it critically depends on the transmission probability, T_WKB. In indirect semiconductor, such as Si and Ge, the BTBT model is very crucial for designing and predicting the device performance. In this paper, we employed the nonlocal BTBT model applied to three-dimensional Ge-Si heterojunction TFET with gate length 10 nm compare with Si TFET by including quantum effects simulation. The results show that the Ge-Si TFET outperforms Si TFET because of the lower bandgap and larger tunneling windows. BTBT generation rates of Ge-Si TFET are higher than Si TFET in the on-state condition. The highest BTBT generation rates are located in the source and channel junction and its peaks close to the gate dielectric.

A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high I_ON/I_OFF current ratio of >10⁸. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (V_TH) variation and negligible drain-induced barrier lowering (DIBL < 0.4 mV/V). The reported device with the thinnest channel has a very high band-to-band tunneling generation rate of 1.2 × 10²⁴/cm² s when the channel is scaled down to <1 nm, as confirmed by using the 3D quantum transport simulation tool. This quantum tunneling provides a means of achieving an SS value much lower than its fundamental physical limit.

This comprehensive study of the horizontally p-type stacked nanosheets inversion mode thinfilm transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS-TFT) structures. The stacked nanosheets device structure, fabrication, and electrical characteristics are analyzed. The SNS-GAATFT reveals better performance to multi-gate SNS-TFT. The proposed inversion mode SNS-TFT has properties of the easy process with low cost and compatible with all 3-D Si CMOS and AMOLED applications. Moreover, the SNS-GAATFT is suitable for future monolithic 3-D IC for 2015's ITRS technology roadmap for the year 2024-2030.

This work demonstrates the gate-all-around P/N hybrid nanosheet (NS) p-channel junctionless field-effect transistors (GAA NS-JLFET) with trench and raised source and drain structure. The GAA NS-JLFET exhibits the superior electrical properties, including high field-effect mobility (18.9 cm2/Vs), high ON/OFF current ratio (>5$\times10^6$), steep subthreshold slope (136 mV/dec.), and low DILB (60 mV/V). The high mobility and steep subthreshold slope (SS) of this GAA NS-JLFET indicates that the conducting hole filled the whole thin nanosheet channel. This GAA NS-JLFET is simple to fabricate and highly favorable for use in advanced system-on-panel (SoP) and three-dimensional (3-D) stacked ICs applications.