We fabricated the HfZrO ₂ (HZO) ferroelectric fin field-effect transistors (Fe-FinFET) with fin width of 60 nm and gate length of 100 nm for ferroelectric nonvolatile memory operations. The fabricated Fe-FinFET exhibited a large memory window (MW) of 1.5 V and high (100 ns) program/erase speeds at ±5 V. After 10 ⁵ program/erase cycles, the MW was maintained at 1.09 V and the retention time was measured up to 10 ⁴ s with no degradation. The fabricated HZO Fe-FinFET is compatible with the current FinFET process and has a high MW, a fast program/erase speed, and excellent reliability. Therefore, the fabricated Fe-FinFET is a promising candidate for high-density ferroelectric field-effect transistor memory applications.

Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more $\text{W}_{\mathrm{ eff}}$ per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio ( $> 10^{8}$ ), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices.

A polycrystalline silicon (poly-Si) channel twin thin-film transistor (twin-TFT) nonvolatile memory (NVM) device with In-Ga-Zn-Ox (IGZO) as a storage layer is demonstrated. IGZO-FG twin-TFT NVM exhibits a large memory window ΔV_th. A V_CG at 18 V for 10 ms can achieve 5.6 V of ΔV_th. An extrapolation of the memory window to ten years demonstrates that the stored charge still remains 65% of its initial value. Coupling ratio effect and gate length effect are discussed in detail. Such a low-temperature IGZO-FG twin-TFT NVM device is feasible for integration in IGZO-based display circuits for system-on-panel applications.

This investigation examines polycrystalline silicon thin-film transistors (TFTs) with multiple nanowire channels and a lightly doped drain (LDD). A device with an LDD structure exhibits low leakage current because the lateral electrical field is reduced in the drain offset region. Additionally, multiple nanowire channels can generate fewer defects in the polysilicon grain boundary and have more efficient ${\mathrm{NH}}_3$ plasma passivation than single-channel TFTs, further reducing leakage current. They exhibit superior electrical characteristics to those of single-channel TFTs, such as a higher ON/OFF current ratio ${\text{(>10}}^8\mathrm{),}$ a better subthreshold slope of 110 mV/decade, an absence of drain-induced barrier lowering, and suppressed kink-effect. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal display technologies.

A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high I_ON/I_OFF current ratio of >10⁸. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (V_TH) variation and negligible drain-induced barrier lowering (DIBL < 0.4 mV/V). The reported device with the thinnest channel has a very high band-to-band tunneling generation rate of 1.2 × 10²⁴/cm² s when the channel is scaled down to <1 nm, as confirmed by using the 3D quantum transport simulation tool. This quantum tunneling provides a means of achieving an SS value much lower than its fundamental physical limit.