Kunyu Wang

Mr. Kunyu Wang

orcid

Research Focus & Metrics

Academic Career Length

5Years (2022-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 March 2024 in Chinese Journal of Electronics
Verified
Journal Article
Closed access
KWKunyu Wang
Kunyu Wang
WXWenjing Xu
Wenjing Xu
CZChengbin Zhang
Chengbin Zhang
YYYanjun Yang
Yanjun Yang
MLMan-Kay Law
Man-Kay Law
MCMing Chen
Ming Chen
A high dynamic range and low-noise CMOS (complementary metal-oxide-semiconductor transistor) front-end interface integrated circuit (IC) with multi-channel detection is presented in this paper. Two different current detection channels, composed of a trans-impedance amplifier (TIA) and an integrator-differentiator TIA, are used to boost the current detection range. A capacitance-coupled instrument amplifier (CCIA) is also included to realize high precision voltage detection. A fourth-order sigma-delta modulator using a second-order loop filter and a second-order noise shaping integral quantizer is adopted to realize effective number of bits above 16 bits. The presented interface IC is implemented in 0.18-μm CMOS process with supply voltage of 3.3 V, and a proto-type electrochemical sensor platform with miniaturized sensor array is developed to verify the functionality of the interface IC. Measurement results indicate that the designed interface IC achieves 157.8 dB current detection dynamic range, and the measured input-referred current noise and voltage noise floor are 1.04 pA and 58.4 nV within 10 kHz integration bandwidths, respectively.

22 September 2022 in Electronics
Verified
Journal Article
Open access
PDF file
YLYange Lu
Yange Lu
MCMing Chen
Ming Chen
KWKunyu Wang
Kunyu Wang
YYYanjun Yang
Yanjun Yang
HWHaiyong Wang
Haiyong Wang
The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.