The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

High-bandwidth interconnects between chiplets employ parallel interfaces, whose performance is limited by inter-channel crosstalk. In order to reduce the delay uncertainty (jitter) induced by crosstalk, this work analyzes the effect of signal skew and proposes a static skew scheme and a novel dynamic skew scheme. A fast algorithm is also suggested to determine the optimal skew value for the dynamic scheme. The experiment results show that the static scheme can significantly reduce jitter for low-speed buses but fails at high speed. By contrast, the dynamic scheme reduces jitter by about 44% for low-speed buses, reduces the jitter increment due to intersymbol interference by about 71%, and is effective at a higher bus rate. The proposed signal skew schemes require no additional routing overhead.