A high dynamic range and low-noise CMOS (complementary metal-oxide-semiconductor transistor) front-end interface integrated circuit (IC) with multi-channel detection is presented in this paper. Two different current detection channels, composed of a trans-impedance amplifier (TIA) and an integrator-differentiator TIA, are used to boost the current detection range. A capacitance-coupled instrument amplifier (CCIA) is also included to realize high precision voltage detection. A fourth-order sigma-delta modulator using a second-order loop filter and a second-order noise shaping integral quantizer is adopted to realize effective number of bits above 16 bits. The presented interface IC is implemented in 0.18-μm CMOS process with supply voltage of 3.3 V, and a proto-type electrochemical sensor platform with miniaturized sensor array is developed to verify the functionality of the interface IC. Measurement results indicate that the designed interface IC achieves 157.8 dB current detection dynamic range, and the measured input-referred current noise and voltage noise floor are 1.04 pA and 58.4 nV within 10 kHz integration bandwidths, respectively.

The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

This paper presents a discrete-time (DT) 4^th-order ΔΣ modulator using a 2^nd-order noise-shaped integrating quantizer (NSIQ). By adding a passive finite impulse response (FIR) filter to the 1^st-order NSIQ, the proposed quantizer has obtained 2^nd-order noise shaping ability, without extra power consumption. By incorporating the digital integrator, the linearity requirement of the quantizer is relaxed. The proposed modulator is fabricated in a 0.18 μm CMOS process, and operates at 1 MS/s achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 106.9 dB in a 10 kHz bandwidth while consuming 240 μW with 1.8 V power supply.