Conventional reflow method in a convection oven is the principal step during the package assembly process in order to guarantee high productivity and make full use of the self-alignment. The package behavior, especially warpage, has significant effects on assuring package assembly reliability during the reflow process. In recent decades, several techniques, like Shadow Moiré or 3-D digital image correlation (DIC), have been developed to assist industry in characterizing warpage. The requirement of artificial speckles on the specimen surface inevitably reduces the measurement accuracy and contaminates the specimen. To improve the accuracy and keep the specimen clean, a novel in situ warpage measurement method without surface treatment is developed, and its result is demonstrated. The specimen can be reapplied to the manufacturing process after the measurement, and one sample can be assessed consistently at different assembly process steps instead of wasting samples at each assembly stage.

Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.

Wafer dicing is a necessary and important process in the microelectronics fabrication. Emerging technologies of IC semiconductor have been utilizing silicon-on-insulation (SOI) wafers. These wafers have made wafer dicing quite challenging. Compared to conventional blade dicing, stealth dicing has advantages such as debris-free and dry process. MEMS dies that are fabricated on a SOI wafer and then undergo stealth dicing is studied in this paper. Cracks were found around the edges of the membrane in the MEMS dies after stealth dicing. The failure causes are to be determined. Three processes in the stealth dicing are studied: IR laser scanning, tape dicing and peeling process. Effects of these three processes on the die stresses were investigated. It is the first time that die stresses in a membrane-structured MEMS on SOI wafer in stealth dicing are analyzed. Thermal/structural stress contours are obtained by finite element analysis. Die stresses caused by these three processes are compared.