Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

Moisture can have significant effects on the performance and reliability of electronic components. Accurately simulating moisture diffusion is important for designers and manufacturers to obtain a realistic reliability evaluation. Beginning with version 14, ansys is capable of simulating diffusion and related behaviors, such as hygroscopic swelling, with newly developed elements. However, a normalized approach is still required to deal with the discontinuity of concentrations at the material boundaries, and normalization of the moisture concentration in transient thermal conditions is tricky. Case studies have shown that normalizing the moisture concentration with respect to a time- or temperature-dependent material property will lead to erroneous results. This paper re-addresses the issues of performing diffusion simulations under transient thermal conditions and more general anisothermal conditions (temporally and spatially), and suggests an easy-to-use approach to cope with the limitations of the current version for users in the electronic packaging industry.

Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.