Conventional reflow method in a convection oven is the principal step during the package assembly process in order to guarantee high productivity and make full use of the self-alignment. The package behavior, especially warpage, has significant effects on assuring package assembly reliability during the reflow process. In recent decades, several techniques, like Shadow Moiré or 3-D digital image correlation (DIC), have been developed to assist industry in characterizing warpage. The requirement of artificial speckles on the specimen surface inevitably reduces the measurement accuracy and contaminates the specimen. To improve the accuracy and keep the specimen clean, a novel in situ warpage measurement method without surface treatment is developed, and its result is demonstrated. The specimen can be reapplied to the manufacturing process after the measurement, and one sample can be assessed consistently at different assembly process steps instead of wasting samples at each assembly stage.

The decreasing size of solder joints leaves limited tolerance of allowable warpage range for successful assembly. Understanding the electronic packages' behavior during the reflow process becomes one of the most important tasks in developing assembly process and assuring reliability. Three-dimensional (3D) digital image correlation (DIC) plays an important role in quantifying warpage of BGA packages under thermal loading. To measure warpage of the substrate surface of a BGA package, conventional 3D DIC technique requires removing the solder balls, which takes the risk of damaging the solder mask surface and influences on measurement accuracy. Three parameters of 3D DIC (camera angle, facet size and facet step) are studied on the effects of data integrity and accuracy to realize warpage measurement while solder balls are attached to the packages. This method introduces novel settings of these parameters compared to current 3D DIC requirements, and summarizes a guidance for implementing nondestructive warpage measurement with different sizes of solder balls and camera resolutions.

Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.