This paper presents a chip-scale ultralow quiescent current power management system that interfaces with electromechanical energy harvester for enabling self-powering, batteryless wireless sensors. A piezoelectric transducer scavenges and transforms mechanical vibration energy into electricity in ac form, which is then converted into dc power by a full bridge rectifier and collected into a small filter capacitor. A buck-boost converter, as an impedance matching converter to achieve maximum power point tracking, further transfers the energy into a supercapacitor, from which a low-dropout (LDO) regulator powers an on-chip CMOS sensor with clean power supply. Additionally, the energy stored in the supercapacitor can be used to drive a radio frequency transmitter. These components form a complete wireless sensor node, applicable for the Internet of Things sensor networks. The chip is fabricated by using a standard 0.5 μm CMOS process. From measurements we have verified all the key merits of this design: first, a high voltage converting efficiency (up to 97.1%) of the rectifier; second, a minimum of 102 s charging time to charge a 1 mF supercapacitor from 0 to 3.3 V of the buck-boost converter with impedance matching method; and third, a 10 nA to 100 μA load current range and at least 85° phase margin LDO regulator with ultralow quiescent bias current as low as 750 pA.

In this paper, a proof-of-concept high-efficiency rectifier-booster regulator (RBR) with an impedance matching converter operating at 2.45 GHz is proposed. An entire WLAN energy harvesting system is demonstrated. A flower-shaped broadband dual-polarized cross dipole antenna with a full-wave matching network is employed to harvest electromagnetic energy from a WiFi router. A novel RBR is proposed to rectify the RF energy to dc and boost the output voltage. It is evolved from a Greinacher rectifier and two Cockcroft-Walton charge pumps to form a full-wave rectifier. An equivalent resistance model is established to evaluate the optimal stage of the RBR. Furthermore, a boost converter is designed as an impedance matching converter to harvest as much energy as possible from the RBR and store the energy into a 1-mF supercapacitor. Experimental results show that the RBR can provide 1.7-V output voltage under -10-dBm input power. In addition, the RBR can achieve up to x 3.4 voltage boosting with 85% voltage conversion rate (VCR) and provide a higher than 1-V output voltage within a distance of 50 cm between an antenna with 20-dBm transmitting power and the rectenna. The excellent performance shows the wide practicality of the proposed design method for the Internet-of-Things (IoT) applications.

To reduce multiplication operations in convolution of convolutional neural networks (CNNs), there are three widely used convolutional acceleration algorithms, i.e., Winograd, FFT and FFA. However, current accelerators based on these convolutional acceleration algorithms have issues on flexibility and efficiency. Firstly, some accelerators utilized a combination of these acceleration algorithms and employed multiple types of computational units to achieve their respective advantages. As a result, some computational units are left unused when the best-performing unit is working, which causes much area inefficiency. Secondly, current accelerators tend to choose small parameters of these convolutional acceleration algorithms to avoid unacceptable precision loss, as a result, they are hardly to support large kernel sizes and lack of flexibility. Thirdly, these acceleration algorithms are typically presented for 1-stride convolutions, consequently, few implementation considers the acceleration of large-stride convolutions, which is a major restriction to hardware flexibility. This paper proposed a stride-based convolution decomposition method (SCDM) to reform different convolution shapes (i.e., kernel sizes & strides) to an identical pattern. With the aid of SCDM, a Winograd-stretched and hardware-efficient design (WHD) is presented to utilize one uniform computational unit for the acceleration of different convolution shapes, which combines complementary performance advantages on both Winograd F(4,3) and F(4,2) units. Compared to current FFT-based or FFA-based works, WHD can stretch the use range of Winograd and simplify implementation, thereby achieving hardware flexibility and efficiency. Evaluation results show that 34.08%~55.41% operation reduction were achieved on six CNN models, while incurring a slight hardware overhead.

As convolutional neural networks (CNNs) become more and more diverse and complicated, acceleration of CNNs increasingly encounters a bottleneck of balancing performance, energy efficiency, and flexibility in a unified architecture. This paper proposed a Winograd-based highly efficient and dynamically Reconfigurable Accelerator (named WRA) for quickly evolving CNN models. A cost-effective convolution decomposition method (CDW) was proposed, and it extends the application of the fast Winograd algorithm. Based on CDW, a high-throughput and reconfigurable processing element (PE) array was designed to exploit the parallelism of Winograd. Besides, a highly compact memory structure employed four levels of data reuse schemes to achieve maximal data reuse and minimize external bandwidth requirement. Provided with dynamically reconfigurable capability, WRA implements CDW and other convolutions (e.g., standard convolution, depthwise separable convolution, and group convolution) on a unified hardware architecture. The WRA accelerator was implemented on a Xilinx XCVU9P platform running at 330 MHz clock frequency, controlled by a POWER8 processor via a coherent accelerator processor interface (CAPI) interface. At different configurations, WRA can provide 2.2–6.3 TOPS performance for different convolution shapes. The average performance and energy efficiency for VGG16/AlexNet/MobileNetV1/MobileNetV2 are 5288 GOP/s at 151.2 GOPs/W, 3478 GOP/s at 99.4 GOPs/W, 2674 GOP/s at 76.4 GOPs/W, and 2194 GOP/s at 62.7 GOPs/W. It achieves $1.7\times $ – $24\times $ speedup compared with the previous FPGA-based designs.