Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology. Graphical Abstract

Constrained by the transimpedance limit, the conventional 1-stage shunt-feedback transimpedance amplifier (1S-SF-TIA) suffers poor noise and gain at higher data rates. In this paper, we propose to use a multi-stage stagger-tuned amplifier (MSTA) to constitute TIA (MSTA-TIA), which not only transcends the transimpedance limit of 1S-SF-TIA, but also realizes noise reduction in multiple fronts. First, the high-gain MSTA enables 17X TIA gain over 1S-SF-TIA, which effectively suppresses the white noise. Second, the MSTA realizes at least 2.8X~1.6X lower noise than the conventional multi-stage amplifier, which is essential to form low-noise TIA since the amplifier noise usually dominates. Third, the TIA built upon the 3-stage STA also shows steeper out-of-band roll-off to enable high-frequency noise reduction. Overall, the MSTA-TIA achieves 6.9X and 1.9X noise power reduction over conventional single-stage and multi-stage SF-TIAs. As a demonstration, a 10 Gb/s optical receiver front-end prototype employing proposed MSTA-TIA topology is implemented in a standard 0.18μm CMOS technology. It achieves transimpedance gain of 68.3dBΩ , electrical bandwidth of 8.5GHz, and excellent input-referred noise current of 0.97μArms. The chip occupies 0.78 mm² while consuming 43 mA from 1.8 V power supply. The low-noise design methodology in this paper empowers mature CMOS to compete with SiGe to make low-noise high-gain optical IC.

Boost converter often exhibits large output voltage ripples and slow transient response due to the pulsating output capacitor current and the right-half-plane zero in transfer function from duty ratio to output voltage. On the contrary, a KY converter shows small output voltage ripples and fast transient response compared with the boost converter thanks to its buck-converter-like characteristics. In this study, a comprehensive study of an integrated KY converter considering parasitic resistance is presented as design guidelines for its IC implementation, and various aspects of KY converter versus boost converter are also analyzed to show its advantages. In particular, optimum transistor sizes, power losses, and output voltage ripples are analyzed in depth. The designs of power components including energy-transferring capacitor, inductor, and filter capacitor are discussed. Theoretical derivations of load and line regulations are also provided. The designed KY converter has been fabricated with standard 0.18-μm CMOS process and the total chip area is 1.93 mm ² including pads. The output voltage is 2.5 V with the regulated supply voltage ranging from 1.55 to 1.8 V, at switching frequency of 1 MHz. The output voltage ripples are 10 mV. Maximum efficiency of 95.7% is obtained at load current of 55 mA and supply voltage of 1.8 V. Efficiency is no less than 92.9% for load current as low as 30 mA. Even with simple compensation scheme employed, the output voltage settles within 48 μs when loading a step current of 150 mA.

Noise probably the single most important performance metric of the high-speed transimpedance amplifier (TIA), which directly sets the sensitivity of optical receiver. The transimpedance limit which dictates the maximum achievable transimpedance gain of the TIA also turns out to fundamentally limit the TIA noise performance. In this tutorial, we analyze and explore two circuit design approaches to overcome the transimpedance limit. The first approach (Type I) realizes a divide-and-conquer methodology to separate the noise-bandwidth problem and solve them individually. The second approach (Type II) employs a multi-stage stagger-tuned amplifier. Both approaches can overcome the transimpedance limit, forming an effective toolkit for the design of low-noise high-speed TIA for high-sensitivity CMOS optical receivers in current and future applications.