This brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise and ultra-low power performance. By employing the mixed switching scheme, the segmented capacitive digital-to-analog converter (CDAC) arrays as well as the synchronous data-weighted averaging (DWA) calibration block, the proposed SAR ADC can operate from 1.8 V down to 0.8 V at 20–200 kS/s. The designed ADC is fabricated in a 0.18- $\mu {\mathrm{ m}}$ CMOS process and the measurement results show the proposed SAR ADC achieves an SNDR of 65-dB with power consumption of 647 nW from a 0.8 V power supply at 20 kS/s.

Multiple loops have been used extensively to enhance the system performance in various applications. However, the increasing complexity of multi-loop systems also makes them much more difficult to analyze and implement. In this paper, a new methodology to analyze multi-loop system is proposed. In the proposed framework, multi-loop systems are regarded to be built upon of sub-modules of cascade, parallel adding, and feedback units, and then, they are simplified following a certain procedure based on the correlation of the Bode characteristics of the segmented sub-modules. Applying this methodology, the Bode plot and the transfer function of the system can be easily obtained with the system properties of gains, zeros, and poles. Two examples are provided as demonstrators, including a multi-loop low-dropout regulator (LDO) from literature, and a newly designed multi-loop LDO aiming at enhancing the stability over a wide load range, which show that the Bode plot and the transfer function can be obtained more intuitively and rapidly. Excellent agreements among theory, simulations, and measurements are confirmed, which verify the proposed method. It can help designers to gain more intuitions and insights on multi-loop systems from both circuit and device perspectives, which is also an effective tool for both stability analysis and circuit design.

Circulator is a key component in full-duplex wireless and radar detection systems. In this letter, a dual interference-canceling active quasi-circulator is proposed to enhance the isolation capability over the range of 1-7 GHz. The circulator is fabricated in the standard 0.18-μm CMOS process occupying 1.03 mm x 0.55 mm including the pads. Measurement results demonstrate more than 36-dB isolation from the Tx to the Rx within 6-GHz bandwidth. The designed circulator is a good candidate for duplexers to allow the integrated transmitter and receiver to share a single antenna in the certain short-range wideband wireless communication systems, where noise figure (NF) is not strictly demanded but low cost and high integration are urgently required.

The effects of supply-induced frequency variations on single-ended tuning LC voltage-controlled oscillator (VCO) which degrade the jitter performance of the clock are investigated. The first-order impact on the supply sensitivity is that the varactor's effective capacitance varies with the supply voltage, with other second-order impacts attributed to commonly used capacitive bank and cross-coupled pairs. A compensation technique based on complementary varactors to improve the supply sensitivity of single-ended tuning LC VCO is proposed with no extra power dissipation, nor phase noise degradation within the relative frequency band of interest, along with the discussion on the operating principle of the compensation technique. Both the NMOS cross-coupled and complementary cross-coupled LC VCOs have been designed, demonstrating robust supply-insensitive performance over process, voltage, and temperature (PVT) variations. Prototyped oscillators were fabricated in a 0.18-μm CMOS process to verify both the theoretical analysis and the effectiveness of the proposed technique. Measurement results show that the compensated topologies exhibit more than 93% reduction in periodic jitter versus the noncompensated counterparts, with the figures of merit (FoMs) among the best compared with previous supply insensitive works.

This letter presents a 5–6-GHz CMOS beamforming transceiver front-end with high linearity and low power consumption for fiber-to-the-room (FTTR) all-optical Wi-Fi solution, which can greatly reduce the transmission power and eliminate signal mutual interference among access points compared with traditional architecture, by aggregating beams of multichannel. The transmitter (TX) employs a high-linearity power amplifier, a variable-gain amplifier, a 5-bit passive attenuator (ATT), and a 4-bit passive phase shifter (PS). The receiver (RX) is composed of a single-to-differential variable gain low-noise amplifier (LNA), frequency-tuning buffers, a 5-bit ATT, and a 4-bit PS. Implemented in a 55-nm CMOS technology, the measured output power 1dB compression point (OP1dB) of TX is better than 12.1 dBm. The error vector magnitudes (EVMs) of the TX at 0-dBm output power with 80-MHz 256-quadrature amplitude modulation (QAM) orthogonal frequency division multiplexing (OFDM) signal are better than $-$ 36.3 dB, and the EVMs of the RX at $-$ 40 dBm input power are better than $-$ 37.8 dB. The noise figure is 4.3 dB in high-gain mode.