In this paper, we systematically evaluate dc/ac performances of sub-7-nm node fin field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) using fully calibrated 3-D TCAD. The stress effects of all the devices were carefully considered in terms of carrier mobility and velocity averaged within the active regions. For detailed AC analysis, the parasitic capacitances were extracted and decomposed into several components using TCAD RF simulation platform. FinFETs improved the gate electrostatics by decreasing fin widths to 5 nm, but the fin heights were unable to improve RC delay due to the trade-off between on-state currents and gate capacitances. The NSFETs have better on-state currents than do the FinFETs because of larger effective widths (Weff) under the same device area. Particularly p-type NSFETs have larger compressive stress within the active regions affected by metal gate encircling all around the channels, thus improving carrier mobility and velocity much. On the other hand, the NSFETs have larger gate capacitances because larger Weff increase the gate-to-source/drain overlap and outerfringing capacitances. In spite of that, sub-7-nm node NSFETs attain better RC delay than sub-7-nm node as well as 10-nm node FinFETs for standard and high performance applications, showing better chance for scaling down to sub-7-nm node and beyond.

In this paper, multi-threshold voltage ( V _th ) scheme of 7-nm node nanosheet FETs (NSFETs) with narrow NS spacing were successfully achieved by metal-gate work function (WF) and channel doping ( N _ch ) using fully calibrated 3-D TCAD simulations. The limited NS spacing, which allows TiN capping layer only, makes different WF between the edge and the middle part of NS circumference. Unfortunately, this causes non-linear Vth shifts and dc performance degradation as a function of WF due to one-side turn-on phenomena between the edge and the middle part. Furthermore, the fixed WF of TiN capping layer limits Vth shifts toward ultra-low-power applications. To enable multi-Vth of NSFETs, several possible solutions are addressed: changing the Nch and the WF of TiN capping layer. The higher N _ch enables lower off-state current while 50-nm-wide three-stacked NS decreases dc performance variations effectively. Changing the WF of TiN capping layer can extend V _th margins, but degrade DC performance as a trade-off. Nonetheless, 7-nm node NSFETs adopting these techniques have multi- V _th options to satisfy wide ranges from ultra-low-power to high-performance applications.

Process (systematic) variations of sub-5-nm node fin field-effect transistors (FinFETs) and nanosheet field-effect transistors (NSFETs) were investigated thoroughly using fully calibrated TCAD. All the process parameters consisting of front-end- as well as middle-of-line structure were independently randomized within feasible process conditions. A novel process scheme called source/drain patterning (SDP), having a superior performance by decreasing outer fringing capacitance through the downsized source/drain (S/D) epi, has also been analyzed for the variability study. SDP FinFETs have smaller variations of threshold voltages (Vth), off-state currents (Ioff), and effective currents (Ieff) than conventional ones because the subfin leakage is effectively controlled by bottom oxide (BO) beneath the source/drain instead of high punchthrough-stopper doping. The Spearman's correlation results between process parameters, Ioff, and Ieff, showed that the process parameters affecting the short-channel effects vary Ioff and Ieff greatly. Especially, the most critical one was the fin width (Wfin) for FinFETs. SDP NSFETs have the smallest variations of Vth, Ioff, and Ieff. The BO blocks the bottom leakage completely, and the variations of nanosheet (NS) thickness (TNS) are much smaller than those of Wfin due to the different process flows: epitaxial growth for TNS versus patterning for Wfin. Therefore, NSFETs are promising to reduce the variations of Vth, Ioff, and Ieff in the sub-5-nm node.

Excess source and drain (S/D) recess depth (TSD) variations were analyzed comprehensively as the most critical factor to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. The variations of off-, on-state currents (Ioff, Ion) in three-stacked NS channels and parasitic bottom transistor (trpbt), gate capacitance (Cgg), intrinsic switching delay time (td), and static power dissipation (Pstatic) are investigated quantitatively according to the TSD variations. The more S/D dopants diffuse into the trpbt with the deeper TSD, so the Ioff and Ion increase by raised current flowing through the trpbt. Especially, the Ioff of PFETs remarkably increases above the certain TSD (TSD,critical) compared to NFETs. Furthermore, the Ion contribution of each channels having the TSD,critical is the largest at the top NS channel and the trpbt has the ignorable Ion contribution. Among the NS channels, top (bottom) NS channel has the largest (smallest) Ion contribution due to its larger (smaller) carrier density and velocity for both types of NSFETs. The Cgg also increases with the deeper TSD by increasing parasitic capacitance, but fortunately, the td decreases simultaneously due to the larger increase rate of the Ion than that of the Cgg for all SoC applications. However, the Pstatic enormously increases with deeper TSD, and low power applications are more sensitive to the TSD variations than other applications. Comprehensive analysis of the inevitable trpbt effects on DC/AC performance is the most critical indicator whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.

Source/drain (S/D) variations in sub-5-nm node fin and nanosheet field-effect transistors (NSFETs) were thoroughly analyzed by using fully calibrated technology computer-aided design (TCAD). S/D open and contact critical dimensions (OCD and CCD) vary during anisotropic etching for silicide and S/D epi formations, respectively, and these vary dc/ac performances. OCD varies S/D resistances and parasitic capacitances, but slight RC delay variations occur. CCD affects OFF-state currents (IOFF) and RC delay, but differently in terms of fin field-effect transistors (FinFETs) and NSFETs. As the S/D epi enlarges by CCD changes, high subfin leakage of FinFETs flows into the fin bottom regions, thus varying IOFF greatly. NSFETs have the dielectric layers beneath the S/D epi; therefore, the IOFF variations are smaller. Both effective currents (Ieff) and gate capacitances (Cgg) of FinFETs vary in the same direction, whereas the NSFETs have constant Cgg with respect to CCD changes because of the tradeoff between the intrinsic and parasitic capacitances. Although this effect increases the RC delay variations of the NSFETs, p-type FinFETs have the largest RC delay variations due to the greatest relative variations of Ieff. Thus, the NSFETs are much immune to CCD variations compared with FinFETs in terms of IOFF and RC delay.

A novel and feasible trench inner-spacer (TIS) scheme to eliminate undesired parasitic bottom transistors (trpbt) in gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) is proposed based on fully calibrated Technology Computer-Aided Design (TCAD) simulation. Highly doped punch-through stopper (PTS) layers are generally used to suppress trpbt. Unfortunately, trpbt is still a fatal failure factor in electrical performance degradation when the source/drain (S/D) recess is overetched. Moreover, the proposed TIS scheme prevents the diffusion of S/D dopants toward the PTS region beneath the bottom gate, thereby inhibiting the formation of trpbt. Furthermore, the TIS-NSFETs exhibit excellent immunity to overetched S/D recess depth variations. Additionally, the thermal characteristics of the TIS scheme are compared to that of the bottom oxide (BOX) scheme forming dielectrics beneath the S/D epitaxies, one of the methods used to suppress trpbt. Lattice temperature caused by self-heating and thermal resistance in the TIS-NSFETs are much lower than that in the BOX-NSFETs for both n/p-type devices. The thermal advantage of TIS-NSFETs compared to BOX-NSFETs is confirmed in both DC and AC conditions, similar to an actual operating environment. Therefore, the proposed TIS scheme is highly recommended to eliminate the undesired trpbt without critical DC/AC degradation and to resolve poor heat dissipation problems in the BOX scheme simultaneously.