Transient pulses generated by high-energy particles can cause soft errors in circuits, resulting in spacecraft malfunctions and posing serious threats to the normal operation of spacecraft. For integrated circuits used in space applications, it is necessary to first evaluate soft errors caused by transient pulses. Conventional soft-error-rate evaluation tools are designed to simulate the generation of transient pulses using many accurate models, while the propagation of transient pulses is primarily simulated by circuit-level simulation tools. Due to the limitations of simulation tools, conventional evaluation approaches are limited to the circuit scale. The simulation runtime is unbearable for large-scale integrated circuits. This paper presents an approach for evaluating the soft error rate using machine learning. A back propagation neural network is implemented in the proposed approach. It helps to determine the probability of transient pulse propagation. Compared with the conventional soft-error-rate evaluation results, the proposed approach demonstrates a strong correlation in both trend and magnitude. The average difference between the results obtained using the proposed evaluation method and the experimental results is 23.5%, which is 7.5% higher than that between the results obtained using the conventional evaluation method and the experimental results. Compared to the conventional evaluation method, the proposed approach improves the runtime by an order of magnitude. The proposed approach also benefits the locating of highly sensitive circuit nodes in large-scale integrated circuits. Circuit design and radiation hardening are both useful applications.

The static random-access memory (SRAM) physical unclonable function (PUF) uses the power-up states of stored values to derive the identification code. Its lightweight circuit design makes it suitable for power-sensitive satellites. However, the SRAM PUF is significantly affected by high-energy particles and cosmic rays in space, which causes incorrect output of identity authentication codes and further leading to a degradation in reliability. Recently, the main research works are concerned about the impact of cosmic rays induced total ionizing dose effects on the SRAM PUF, and few reports discuss the high-energy particles induced single event effects on the SRAM PUF. This paper presents the reliability results of planar and FinFET-based SRAM PUFs after high-energy heavy ion experiments. Experimental results indicate that 3%–10% of the SRAM PUF bits change from their original power-on states, which demonstrate that ion-induced microdose effects degrade the reliability of SRAM PUFs. In addition, the three-dimensional technology computer-aided design simulation tool is used to analyze the physical mechanisms of the experimental phenomena. Simulation results show that the heavy ion-induced microdose effect ionizes and produces trapped charges at the silicon/insulation interface, which causes a slight change in transistor leakage current or a slight drift in threshold voltage. The physical mechanisms lead to an off-state current mismatch in the SRAM cell and finally affect the stored values after power-on.

This paper presents a radiation-hardened flip-flop called MSIFF. The sensitive node-pairs between the master and slave latches are readjusted at layout-level. It obtains a high SEU tolerance with slight area and performance degradation. A test chip was irradiated with the static and dynamic test modes to validate the SEU tolerance of the proposed MSIFF. Experimental results demonstrate superior performance of the MSIFF over the conventional DICE and D flip-flop.

P-hit and N-hit single-event transients are investigated using heavy ion microbeam. A novel layout placement was implemented in the test chip to distinguish SETs originating from P-hit and N-hit. Experimental results indicate both the P-hit and N-hit SETs show an exponential-like distribution in all target circuits. The SET cross sections and the average pulse width for P-hit and N-hit are also investigated. The well process, the transistor size and the layout topology significantly impact on the cross sections. Only the transistor size impacts on the average pulse width at low LET.

The heavy ion-induced sensitive area is an essential parameter for space application integrated circuits. Circuit Designers need it to evaluate and mitigate heavy ion-induced soft errors. However, it is hard to measure this parameter due to the lack of test structures and methods. In this paper, a test method called TAISAM was proposed to measure the heavy ion-induced sensitive area. TAISAM circuits were irradiated under the heavy ions. The measured sensitive areas are 1.75 $\mathsf{\mu }$m${}^2$ and 1.00 $\mathsf{\mu }$m${}^2$ with different LET values. TAISAM circuits are also used to investigate the layout structures that can affect the sensitive area. When the source region of the target transistor is floating, the heavy ion-induced sensitive area decreases by 28.5% for the target PMOS transistor while it increases by more than 28% for the target NMOS transistor. When the well contacts are added, the heavy ion-induced sensitive area decreases by more than 25% for the target PMOS transistor while it remains unchanged for the target NMOS transistor. Experimental results directly validate that the two structures significantly affect the heavy ion-induced sensitive area.