The Industrial Internet of Things (IIoT) paradigm represents a significant leap forward for sensor networks, potentially enabling wide-area and innovative measurement systems. In this scenario, smart sensors might be equipped with novel low-power and long range communication technologies to realize a so-called low-power wide-area network (LPWAN). One of the most popular representative cases is the LoRaWAN (Long Range WAN) network, where nodes are based on the widespread LoRa physical layer, generally optimized to minimize energy consumption, while guaranteeing long-range coverage and low-cost deployment. Additive manufacturing is a further pillar of the IIoT paradigm, and advanced measurement capabilities may be required to monitor significant parameters during the production of artifacts, as well as to evaluate environmental indicators in the deployment site. To this end, this study addresses some specific LoRa-based smart sensors embedded within artifacts during the early stage of the production phase, as well as their behavior once they have been deployed in the final location. An experimental evaluation was carried out considering two different LoRa end-nodes, namely, the Microchip RN2483 LoRa Mote and the Tinovi PM-IO-5-SM LoRaWAN IO Module. The final goal of this research was to assess the effectiveness of the LoRa-based sensor network design, both in terms of suitability for the aforementioned application and, specifically, in terms of energy consumption and long-range operation capabilities. Energy optimization, battery life prediction, and connectivity range evaluation are key aspects in this application context, since, once the sensors are embedded into artifacts, they will no longer be accessible.

Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment.

Event-driven data acquisition is used to capture information from fast transient phenomena typically requiring a high sampling speed. This is an important requirement in the ITER Neutral Beam Test Facility for the development of one of the heating systems of the ITER nuclear fusion experiment. The Red Pitaya board has been chosen for this project because of its versatility and low cost. Versatility is provided by the hosted Zynq System on Chip (SoC), which allows full configuration of the module architecture and the OpenSource architecture of Red Pitaya. Price is an important factor, because the boards are installed in a hostile environment where devices can be damaged by EMI and radiation. A flexible solution for event-driven data acquisition has been developed in the Zynq SoC and interfaced to the Linux-based embedded ARM processor. It has been successfully adopted in a variety of data acquisition applications in the test facility.