PowerSynth is a multi-objective optimization tool for rapid design and verification of power semiconductor modules. By using reduced order models for the calculation of electrical parasitics of the layout and thermal coupling between devices, optimal trace layout and die placement can be simultaneously achieved orders of magnitude faster than conventional finite element analysis (FEA) techniques. An overview of the tool, its modeling methods, model validation, and module layout optimization is presented. The electrical and thermal models are validated against FEA simulations and physical measurements of built modules generated from the tool. The FEA comparisons are performed with FastHenry and ANSYS Icepak to evaluate electrical parasitics and thermal behavior, respectively. A sample hardware prototype based on a half-bridge circuit topology is chosen for testing. Excellent agreement between the FEA simulations, experimental measurements, and PowerSynth predictions are demonstrated. Additionally, when compared with conventional simulation runtime and workflow, PowerSynth takes considerably less computation and user time to produce several candidate layout solutions from which a designer may easily balance selected tradeoffs.

As a critical energy-conversion system component, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the MCPM layout is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with on-going research toward enhanced capabilities to speed up the optimized MCPM layout design process. As a part of this continuing research, in PowerSynth v1.9, a constraint-aware layout engine has been developed, which enables integrating heterogeneous components, handling complex geometry, exploring a larger solution space, improved success rate, and providing options for multiobjective optimization algorithms. The layout engine is generic, scalable, and efficient in performing electro-thermal optimizations on both 2-D and 2.5-D power modules. To validate these enhanced design capabilities, a 2.5-D full-bridge power module layout is designed, optimized, fabricated, and tested with measurement results matching closely with model prediction. This result closes the loop in the power electronics design process with an experimentally validated module design automation flow.

The second Design Automation for Power Electronics (DAPE) workshop was held in the beautiful historical city of Genova, Italy, on 6 September 2019. This was one day after the successful European Conference on Power Electronics and Applications (EPE ECCE). With approximately 40 participants and a nice mix of industry and academic affiliations, the workshop provided outstanding presentations covering the wide field of design automation for power electronics. A very novel exchange of views was performed by breakout sessions, and the use of online voting technology to rapidly poll the attendees on prepared questions of interest in DA provided valuable information (Figure 1).

Moving toward an electrified world requires ultrahigh-density power converters. With the adoption of wide-bandgap semiconductors (e.g., SiC and GaN), the next-generation power converters are on the horizon. However, the complexity of compact and high-speed converters is beyond the current industry-standard design flow based on manual and iterative steps. Therefore, research on design automation and optimization has been identified as an emerging topic in the power electronics society. Among different components of the converter, the physical design of power modules has proven critical for achieving high power density and energy efficiency. We present the latest design automation flow for high-density (2-D/2.5-D/3-D) and heterogeneous multichip power modules (MCPM) through PowerSynth 2 framework. In this article, we further demonstrate electro-thermal optimization for state-of-the-art (SOTA) 3-D packaging technologies. Using the latest PowerSynth 2 framework, electro-thermal design optimization is carried out on a sample 3-D MCPM layout using both exhaustive and evolutionary search methods. The optimized design is hardware-validated against physical measurements. The measurement result has shown an order of magnitude productivity improvement within 10% accuracy compared to the SOTA industry design flow.

This article discusses the challenges in intrachiplet and interchiplet networks, including the need for faster simulation, better architectures, and performance requirements determined by emerging applications.

Recent studies in power electronic design automation have introduced various models for parasitic extraction of multichip power module layouts. However, none of these studies consider the eddy current effect in the direct-bonded-copper substrate, accounting for 40-50% error in the extraction result. This work introduces a methodology for eddy-current consideration through numerical simulation and regression modeling. The regression model utilized in the characterization process in this work is fast and memory-efficient compared to the finite element approach. This characterization process can improve the accuracy of any partial element model without sacrificing performance. Combining this characterization process and partial element approach achieves less than 10% extraction error compared to Ansys Q3D while showing a maximum speed-up of 35× and 17× more memory efficiency. This method also significantly reduces the number of elements in the extracted netlist and the complexity of loop evaluation. This method is attractive for use with optimization routines and therefore has been used successfully in a layout optimization tool.