Sophie Dupuis

Dr. Sophie Dupuis

Microelectronics, Montpellier Laboratory of Informatics, Robotics and Microelectronics, Montpellier, Occitanie, France
orcid

Research Focus & Metrics

Academic Career Length

15Years (2012-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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11 May 2019 in Journal of Electronic Testing
Verified
Journal Article
Closed access
PDF file
Sophie DupuisSophie Dupuis
Sophie Dupuis
MFMarie-Lise Flottes
Marie-Lise Flottes

24 October 2017 in IEEE Design & Test
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Journal Article
Closed access
Sophie DupuisSophie Dupuis
Sophie Dupuis
Marie-Lise FlottesMarie-Lise Flottes
Marie-Lise Flottes
GNGiorgio Di Natale
Giorgio Di Natale
BRBruno Rouzeyre
Bruno Rouzeyre
Due to the evolution in the Integrated Circuit (IC) supply chain, soft/firm/hard cores involved in a system under development and manufactured ICs come from numerous, and possibly unreliable, sources. This loss of control over the entire design/production flow leads to several threats including the insertion by an attacker of malicious circuitries known as Hardware Trojans. Hardware Trojan insertion modifies the functionality of the circuit, possibly its reliability, in order to alter its behavior, generate a denial of service or leak secret information for instance. Numerous methods have been proposed in the literature to detect the presence of such alterations, or prevent their insertion. This paper focuses on methods based on logic testing. Researches in this domain are surveyed and remaining unresolved challenges are described along with proposals to meet these challenges.

2 November 2013 in Information Security Journal: A Global Perspective
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Journal Article
Closed access
Sophie DupuisSophie Dupuis
Sophie Dupuis
GNGiorgio Di Natale
Giorgio Di Natale
Marie-Lise FlottesMarie-Lise Flottes
Marie-Lise Flottes
BRBruno Rouzeyre
Bruno Rouzeyre
International audienceHardware Trojan Horses (HTHs) are malicious and stealthy alterations of integrated circuits introduced at design or fabrication steps in order to modify the circuit's intended behavior when deployed in the field. Due to HTHs stealth and diversity (intended alteration, implementation, triggering conditions), detecting and/or locating them is a challenging task. Several HTHs detection approaches have been proposed to address this problem. This paper focuses on so-called "side-channel analysis" methods, i.e., methods that use power or delay measurements to detect potential HTHs. It reviews these methods and raises some considerations about the experiments made to evaluate them. Moreover, an original case study is presented in which we show that weak experiments may lead to misleading interpretations. Last, we evoke problems inherent to actual power and delay measurements

14 March 2023 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal Article
Closed access
LALevent Aksoy
Levent Aksoy
QNQuang-Linh Nguyen
Quang-Linh Nguyen
FAFelipe Almeida
Felipe Almeida
JRJaan Raik
Jaan Raik
MFMarie-Lise Flottes
Marie-Lise Flottes
Samuel PagliariniSamuel Pagliarini
Samuel Pagliarini
A digital finite impulse response (FIR) filter is a ubiquitous block in digital signal processing applications and its behavior is determined by its coefficients. To protect filter coefficients from an adversary, efficient obfuscation techniques have been proposed, either by hiding them behind decoys or replacing them by key bits. In this article, we initially introduce a query attack that can discover the secret key of such obfuscated FIR filters, which could not be broken by the existing prominent attacks. Then, we propose a first of its kind hybrid technique, including both hardware obfuscation and logic locking using a point function for the protection of parallel direct and transposed forms of digital FIR filters. Experimental results show that the hybrid protection technique can lead to FIR filters with higher security while maintaining the hardware complexity competitive or superior to those locked by prominent logic locking methods. It is also shown that the protected multiplier blocks and FIR filters are resilient to existing attacks. The results on different forms and realizations of FIR filters show that the parallel direct form FIR filter has a promising potential for a secure design.

25 November 2022 in Electronics
Verified
Journal Article
Open access
PDF file
QNQuang-Linh Nguyen
Quang-Linh Nguyen
Sophie DupuisSophie Dupuis
Sophie Dupuis
Marie-Lise FlottesMarie-Lise Flottes
Marie-Lise Flottes
BRBruno Rouzeyre
Bruno Rouzeyre
The current trend to globalize the supply chain in the Integrated Circuits (ICs) industry has raised several security concerns including, among others, IC overproduction. Over the past years, logic locking has grown into a prominent countermeasure to tackle this threat in particular. Logic locking consists of “locking” an IC with an added primary input, the so-called key, which, unless fed with the correct secret value, renders the ICs unusable. One of the first criteria ensuring the quality of a logic locking technique was the output corruption, i.e., the corruption at the outputs of a locked circuit, for any wrong key value. However, since the introduction of SAT-based attacks, resulting countermeasures have compromised this criterion in favor of a better resilience against such attacks. In this work, we propose SKG-Lock+, a Provably Secure Logic Locking scheme that can thwart SAT-based attacks while maintaining significant output corruption. We perform a comprehensive security analysis of SKG-Lock+ and show its resilience against SAT-based attacks, as well as various other state-of-the-art attacks. Compared with related works, SKG-Lock+ provides higher output corruption and incurs acceptable overhead.

3 March 2012 in Integration
Verified
Journal Article
Closed access
Sophie DupuisSophie Dupuis
Sophie Dupuis
RCRoselyne Chotin-Avot
Roselyne Chotin-Avot
HMHabib Mehrez
Habib Mehrez