In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model.

Neural network (NN)-based compact modeling methodologies are gaining attention due to the challenges of device complexity, narrow model coverage, and SPICE simulation speed in advanced semiconductor technology nodes. As device complexity increases, the number of process and structural variables also increases, which significantly increases the amount of technology computer-aided design (TCAD) simulation data required for NN-based compact modeling. This study proposes a multi-fidelity model and active learning approach to predict global and local variations of nanosheet FETs (NSFETs) with less than 1.5% error, significantly reducing the number of required TCAD simulations by more than half compared with conventional modeling techniques. In addition, the simplified NN model with a smaller training dataset significantly reduces the SPICE simulation time.

Emerging transistors lack the statistical compact models needed to evaluate the yield of integrated circuits. To address this, we propose a novel framework combining a variational autoencoder (VAE) and an artificial neural network (ANN). Through the VAE method, a unique set of sources of unexpected process variations in I–V curves can be extracted. Furthermore, the latent vectors serve as inputs to an ANN-based compact model, which enables efficient Monte Carlo (MC) simulations. The proposed ANN-based statistical compact model was experimentally validated using fabricated roll-to-roll (R2R) printed single-walled carbon nanotube thin-film transistors (SWCNT TFTs). The model achieved greater than 98% fit accuracy on measured devices and greater than 90% similarity in key figures of merit (FoMs) in device-level statistical simulations. Our proposed model was implemented in Verilog-A and utilized in SPICE simulations. Our experimental results highlight the framework’s adaptability and efficiency in handling unknown process variations. This data-driven approach for assessing the yield of emerging transistors has the potential to become a cornerstone of future design technology co-optimization (DTCO).

To overcome the difficulty in model parameter extraction and the narrow model coverage of physics-based compact models, artificial neural network-based compact models (ANN CM) have been developed. However, the ANN CM lacks physical consistency and sub-models for circuit simulations. In this work, we propose an innovative hybrid compact model that uses a physics-based compact model as a basis with accurate fitting capability over a wide range using two neural networks (NN). First, a bidirectional physics-based compact model generator neural network (PMG-NN) can automatically extract model parameter sets for both the drain current and gate capacitance within a few minutes. Second, a deep global correction neural network (DGC-NN) corrects the electrical inconsistencies caused by process variations to solve the narrow model coverage issues. The hybrid compact model (Hybrid CM) using DGC-NN can predict I_ds, C_gg, C_gd, and C_gs of TCAD-simulated 3 nm nanosheet FETs (NSFETs) with greater than 98.5% accuracy. The hybrid compact model was implemented using Verilog-A and validated through the Gummel symmetry test and SPICE simulations. This new type of compact model has the potential to be the best solution for efficient process optimization and accurate SPICE simulation in real-world applications.

In this work, we propose a signal integrity and power efficiency optimization framework for high-speed I/O equalizer systems using deep reinforcement learning (DRL) based on a deep double Q-network. Although equalizer techniques have long existed, few studies have systematically optimized the feed-forward equalizer (FFE), decision feedback equalizer (DFE), and continuous-time linear equalizer (CTLE) together, including the high-speed channel properties. This framework determines the parameters of the equalizer architecture to optimize performance metrics such as eye height, eye width, and power consumption. It offers three key advantages: (1) a framework with a scalable deep neural network (DNN) to efficiently model complex design challenges; (2) a future-state technique that mitigates design-space expansion with a minimum number of output neurons; and (3) simultaneous evaluation of power efficiency, unachievable with conventional methods. As a proof of concept, we present the optimization of equalizer architecture using the proposed approach across different high-speed channels, including a backplane and an interference-tolerant channel. Experimental results demonstrate that our approach improves signal and power performance significantly compared to those from conventional methods (e.g., minimum-mean squared error, least-mean squared) and converges much faster than genetic, particle swarm, and Bayesian optimization algorithms.

In this study, a novel dual- k spacer ferroelectric field-effect transistor (FeFET) structure is proposed. By adopting the dual- k spacer for the first time in FeFET, the target memory window (MW) of 0.5 V is achievable at a write voltage of 5 V. The write voltage shows a 2.0-V reduction from 7 V for the low- k spacer FeFET (L-FeFET) and a 1.0-V reduction from 6 V for the high- k spacer FeFET (H-FeFET). The write power of the proposed FeFET was 25.9% lower than that of the low- k FeFET and H-FeFET. These improvements significantly expand the Pareto front and mitigate the effects of trapped charge. The dual- k spacer FeFET structure is a promising candidate for low-voltage and low-power operations.