In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN-based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Optimizing the nonlinear electrical characteristics of sub-3-nm devices requires considerable trial and error. However, due to the complexity of physics and secondary effects, technology computer-aided design (TCAD) simulations are time-consuming. Even with a combination of TCAD and a suitable design of experiments (DOEs), comprehensive exploration of the design space using TCAD is a challenging task. In this study, we propose a device optimization framework that can dramatically reduce the number of TCAD simulations while identifying the optimal device structure. The framework we propose consists of an artificial neural network (ANN)-based objective function derived from a dataset generated by weighted Sobol sampling, a multiobjective Bayesian optimization (MOBO) model for device optimization, and an ANN-based compact model for circuit simulation. The framework produced a device structure that showed a 51.5% performance improvement compared to the best device performance found from individual TCAD simulations of 128 structures. In contrast, the manual determination of a device achieving similar results required more than 2048 TCAD simulations.

Neural network (NN)-based compact modeling methodologies are gaining attention due to the challenges of device complexity, narrow model coverage, and SPICE simulation speed in advanced semiconductor technology nodes. As device complexity increases, the number of process and structural variables also increases, which significantly increases the amount of technology computer-aided design (TCAD) simulation data required for NN-based compact modeling. This study proposes a multi-fidelity model and active learning approach to predict global and local variations of nanosheet FETs (NSFETs) with less than 1.5% error, significantly reducing the number of required TCAD simulations by more than half compared with conventional modeling techniques. In addition, the simplified NN model with a smaller training dataset significantly reduces the SPICE simulation time.

We developed analytical compact models of parasitic resistance and capacitance (RC) for nanosheet field-effect transistors (NSFETs) with metal contact structures. The proposed model accurately captures the number of sheets, sheet geometry, gate, source, drain, and contact sizes. The parasitic resistance model generated in each region was modeled using the transmission line method (TLM) and the spread resistance model. The parasitic capacitance model was modeled using the conformal mapping method based on the distribution of the electric field. The developed models were validated by changing the structural parameters. The proposed models were implemented in Berkeley short-channel IGFET model (BSIM)-common multi-gate (CMG) to enable circuit performance prediction. With our proposed model, we can accurately predict the circuit performance of NSFETs, capturing the recent scaling trends and process variations in the proposed NSFET.

This article presents the accurate compact modeling methodology to optimize the gate-induced drain leakage (GIDL)-assisted erase operation for vertical stack-up, multiple stack, and Z -directional shrink of the 3-D vertically integrated NAND (V-NAND) flash memory. The artificial neural network (ANN) is initially applied in the V-NAND transistors to describe the various GIDL characteristics with channel profile variations. In addition, physics-based RC network models are investigated to accurately model the complex process in the state-of-the-art V-NAND products. All models are implemented in Verilog-A, and the time dynamics of the GIDL-assisted channel potential increase for erase operations are successfully reproduced in the SPICE simulations. This SPICE-compatible compact model is essential to the design technology co-optimization (DTCO) for over 200-layer V-NAND, because the RC delay-related erase failures have become an important issue in the high aspect ratio (HAR) channel holes. Based on the proposed compact model, the highly accurate GIDL-assisted erase simulations are performed, and an erase optimization procedure is demonstrated with GIDL injection level, physical etch limit, and Z shrink rate in the next V-NAND candidate structures. Therefore, this process-aware compact model is a valuable tool for pathfinding activities in the early stage of 3-D V-NAND flash memory development.