In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model.

In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN-based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

This paper presents subthreshold digital circuit design and optimization method using Schmitt trigger logic gates for enhanced electromagnetic immunity. The proposed Schmitt trigger logic gates are based on a buffer design using dynamic threshold-voltage MOS for low-power operation. By expanding the Schmitt trigger to NAND/NOR gate, we can dramatically improve the noise immunity with much lower switching power consumption and significant area reduction compared with CMOS Schmitt triggers, at the expense of a slight increase in delay. Not only for the gate level, but also the circuit level immunity improvement is verified with ISCAS 85 benchmark. In addition, we propose a parameter to determine the optimal noise immunity considering the tradeoff between immunity and performance. By using the proposed parameter, optimal hysteresis can be chosen for the reasonable performance deterioration.

In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet field-effect transistors (NSFETs) by locally inserting an oxide material only under the gate region. NSFETs with punchthrough stoppers (PTSs) doping of the substrate region have been widely adopted to reduce substrate leakage; however, band-to-band tunneling (BTBT) under negative bias remains a serious problem in such devices. By only inserting the oxide material under the gate region, the electric field from the gate to the drain–substrate junction is dispersed. Furthermore, since there is no oxide material under the source and drain (S/D) region, there is no stress reduction along the channel direction coming from the silicon-on-insulator (SOI) structure. We performed technology computer-aided design (TCAD) simulations, and the results show that the proposed structure effectively reduces both the tunneling current in the NSFET with PTS structure and the OFF-current in the NSFET without PTS structure, compared with those of conventional NSFETs.

DC-DC buck converters are widely used in portable applications because of their high power efficiency. However, their inherent fast switching releases electromagnetic emissions, making them prominent sources of electromagnetic interference (EMI). This paper proposes a voltage-controlled buck converter that reduces EMI by using a chaotic pulse-width modulation (PWM) technique based on a chaotic triangular ramp generator. The chaotic triangular ramp generator is constructed from a simple on-chip chaotic circuit linked with a symmetrically triangular ramp circuit. The proposed converter can thus operate in the chaotic mode reducing the EMI without requiring any EMI filters. Additionally, using the triangular ramp signal can relax the requirement for a large LC output filter in chaotic mode. The effectiveness of the proposed scheme was experimentally verified with a chaotic triangular ramp generator embedded in a voltage-mode controller buck converter using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process. The measurement results from a prototype showed that the EMI improvement from the proposed scheme is approximately 14.53 dB at the fundamental switching frequency with respect to the standard fixed-frequency PWM reference case.

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant.