The necessity for clean and sustainable energy has shifted the energy sector’s interest in renewable energy sources. Photovoltaics (PV) is the most popular renewable energy source because the sun is ubiquitous. However, PV’s power transfer efficiency varies with different load’s electrical characteristics, temperatures on PV panels, and insolation conditions. Based on these factors, Maximum Power Point Tracking (MPPT) is a mechanism formulated as an optimization problem adjusting the PV to deliver the maximum power to the load. Under full insolation conditions, varying solar panel temperatures, and different loads MPPT problem is a convex optimization problem. However, when the PV’s surface is partially shaded, multiple power peaks are created in the power versus voltage (P-V) curve making MPPT non-convex. Unfortunately, all optimization strategies for MPPT under partial shading applied in previous works, from traditional techniques to Machine Learning and the recently proposed Nature-inspired algorithms, were either computationally expensive or/and led to extensive power losses. To this end, this work presents an algorithm that builds upon metaheuristic optimization algorithms to reduce their complexity further and mitigate the power losses during power tracking. Our experimental results demonstrated that the proposed algorithm converges faster to maximum power point with lower power losses during tracking compared to two very recently proposed MPPT algorithms under partial shading conditions.

As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for accurate gate modeling. Industrial gate models, however, are precharacterized assuming capacitive loads, which poses significant challenges to the approximation of the highly resistive load interconnect with an effective capacitance (Ceff). In fact, most related works are either computationally expensive or unable to approximate the output slew. Furthermore, they require additional precharacterization and ignore the Miller effect. In this article, we present an iterative methodology for fast and accurate gate delay estimation. The proposed approach accurately computes the driver output waveform, using closed-form formulas to calculate a Ceff per waveform segment, while accounting for their interdependence. Thus, it allows for variable analysis resolution exploiting an accuracy/runtime tradeoff. In contrast to prior works, our approach is compatible with conventional CSMs and considers the impact of Miller capacitance. We evaluate our method on representative driver-load test circuits consisting of interconnects with arbitrary RC characteristics and ASU ASAP 7-nm standard cells. The proposed method achieves 1.3% and 2.5% delay and slew root-mean-square percentage error (RMSPE) against SPICE, respectively. In addition, it provides high efficiency, as it converges in 2.3 iterations on average.

With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ramps, while gate-interconnect interdependencies are stronger. Moreover, efficiency is a serious concern since repeatedly invoking a signoff tool during incremental optimization of modern VLSI circuits has become a major bottleneck. In this paper, we introduce a novel machine learning approach for timing estimation of gate-level stages using current source models and the concept of multiple slew and effective capacitance values. First, we exploit a fast iterative algorithm for initial stage timing estimation and feature extraction, and then we employ four artificial neural networks to correlate the initial delay and slew estimates for both the driver and interconnect with golden SPICE results. Contrary to prior works, our method uses fewer and more accurate features to represent the stage, leading to more efficient models. Experimental evaluation on driver-interconnect stages implemented in 7 nm FinFET technology indicates that our method leads to 0.99% (0.90 ps) and 2.54% (2.59 ps) mean error against SPICE for stage delay and slew, respectively. Furthermore, it has a small memory footprint (1.27 MB) and performs 35× faster than a commercial signoff tool. Thus, it may be integrated into timing-driven optimization steps to provide signoff accuracy and expedite timing closure.

This paper introduces a novel approach towards the statistical analysis of modern high-speed I/O and similar communication links, which is capable of reliably to determine extremely low (~10 -12 or lower) bit error rates (BER) by using techniques from extreme value theory (EVT). The new method requires only a small amount of voltage values at the received eye center, which can be generated by running circuit/system level simulations or measuring fabricated I/O circuits, to predict link BERs. Unlike conventional techniques, no simplifying assumptions on link noise and interference sources are required making this approach extremely portable to any communication system operating with very low BER. Our experimental results show that the BER estimates from the proposed methodology are on the same order of magnitude as traditional time domain, transient eye diagram simulations for links with BER of 10-6 and 10-5 operating at 9.6 and 10.1 Gbps respectively.

The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this paper, we introduce a methodology to automatically synthesize hardware accelerators from OpenCL applications. OpenCL is a recent industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our methodology maps OpenCL kernels into hardware accelerators, based on architectural templates that explicitly decouple computation from memory communication whenever this is possible. The templates can be tuned to provide a wide repertoire of accelerators that meet user performance requirements and FPGA device characteristics. Furthermore, a set of high- and low-level compiler optimizations is applied to generate optimized accelerators. Our experimental evaluation shows that the generated accelerators are tuned efficiently to match the applications memory access pattern and computational complexity, and to achieve user performance requirements. An important objective of our tool is to expand the FPGA development user base to software engineers, thereby expanding the scope of FPGAs beyond the realm of hardware design.

This paper proposes a highly efficient model predictive control (MPC) technique for primary-level control of a hybrid storage system (HSS) in a microgrid with renewables. Generally, active set (AS)-based MPCs are used to control HSSbased microgrid systems, which are computationally complex. The high-complexity prevents making control decisions within the sampling time, which negatively affects the robustness of the control system. Moreover, high complexity necessitates powerful controllers, which increase the system's overall cost and energy consumption. On the other hand, less complex controls, such as supervisory control, reduce the storage system's stability, reliability, and lifetime. The proposed method is a closed-form ASbased MPC that shares the mutual advantages of both AS-based MPC and supervisory controllers with additional robustness. It thus significantly reduces the computational complexity while being stable and reliable, improving storage lifetime, and having higher robustness compared to MPC and supervisory controllers. The proposed method is compared to a modified AS-based MPC recently employed for an HSS microgrid application. The analysis showed that the proposed method could significantly outperform the conventional MPC method in computational complexity and robustness, as well as the supervisory controller in terms of reliability, stability, enhanced battery lifetime, and robustness.