In this letter, we report a detailed experimental investigation of the time-dependent breakdown induced by forward gate stress in GaN-based power HEMTs with a p-type gate, controlled by a Schottky metal/p-GaN junction. When a high stress voltage is applied on the gate, a large voltage drop and an electric field occur in the depletion region of the p-GaN close to the metal interface, promoting the formation of a percolation path. We have investigated the mechanisms underlying the gate breakdown by adopting different stress conditions, analyzing the influence of the temperature, and investigating the activation energy of the traps. In addition, thanks to this approach, the device lifetime has been evaluated and an original empirical model, representing the relationship between the gate leakage current and the time to failure, has been proposed.

In this paper, we present an experimental analysis of the degradation induced by positive bias temperature instability stress in GaN-based power high electron mobility transistors with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, the role of the aluminum content (Al%) in the AlGaN barrier layer on the threshold voltage degradation is investigated by means of constant voltage stress measurements. This has been performed for different process conditions with varying Al content. Main results in this paper demonstrate that when a relatively large positive bias is applied on the gate, two competing trapping mechanisms take place in the AlGaN barrier layer or at the p-GaN/AlGaN interface causing V_TH instability. First, an aluminum independent hole trapping mechanism, caused by elastic tunneling from p-GaN valence band (2-D hole gas), leads to a relatively short-time and recoverable negative V_TH shift. In the second step, defect creation occurs. These additional defects are filled with electrons and cause a permanent or slowly recoverable positive V_TH degradation. The amount of defect creation was dependent on the Al% in the barrier.

In this work we investigate the failure modes of GaN based e-mode transistors with a p-GaN gate, for which the top contact towards the p-GaN is realized with a Schottky metal. First the general performance and stability of the platform will be demonstrated, together with the time dependent dielectric breakdown (TDDB) behavior of the gate. The failure mechanism of the gate has been studied by performing constant voltage stress (CVS) measurements. This has been performed for two different process conditions with varying active Mg concentration. Main results in this paper demonstrate i. Reliable device operation for p-GaN gates with Schottky metal contacts II. TDDB degradation of the gate driven by a percolation path III. The type of percolation path is dependent on the gate processing. Results indicate the formation of a percolation path in the AlGaN barrier, which is demonstrated by experiments and further verified by modelling.

In this article, we present an analysis of the gate degradation induced by long-term forward gate stress in GaN-based power HEMTs with p-type gate, controlled by a Schottky metal-retracted/p-GaN junction. In particular, time-dependent gate breakdown and threshold voltage instability are investigated as function of different geometries, gate biases, and temperatures. The introduction of a gate metal retraction (GMR) process step improves the device lifetime because it suppresses the onset of the leakage current flow occurring at the gate edges for relatively high gate voltage. However, biasing GMR p-GaN HEMT at VG > 8 V and T > 80 °C, a new degradation mechanism shows up, possibly altering the lifetime even at low VG operation. Main results in this article demonstrate that although at high VG and high T, a localized degradation effect ascribed to the device isolation region is responsible for time-dependent gate breakdown, thanks to GMR higher operating voltages compatible with ten-year continuous operation is attained. Finally, the longer device lifetime at moderate VG values brought by GMR allows evaluating the threshold voltage instability for long stress times (≈112 h) at relatively high VG and high T, leading to the observation of a saturation of the long-term positive threshold voltage shift and providing additional information about the underlying physical degradation mechanisms. Overall, the saturated 0.65-V Δ VTH under worst-case condition (VG = 7 V at 150 °C, i.e., corresponding to ten-year lifetime) reveals a reliable and fairly stable technology with respect to forward gate stress.

TCAD modeling of the dynamic threshold voltage shift (hysteresis) occurring under fast sweeping characterization in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) is reported, to the best of our knowledge, for the first time. Dynamic ${V}_{\text{TH}}$ hysteresis has been first experimentally characterized under different sweeping times, temperatures, and AlGaN barrier configurations. Then, TCAD simulations have been carried out, reproducing the experimental evidences and understanding the microscopic mechanisms responsible for such effect. In particular, nonlocal tunneling models implemented in Sentaurus TCAD, defined at the gate Schottky contact and assisted by traps in the AlGaN barrier layer, have been adopted and properly tuned against experiments. Results show that the dynamic ${V}_{\text{TH}}$ hysteresis is mainly caused by the time-dependent hole charging/discharging processes in the floating p-GaN layer, which are governed by the Schottky and AlGaN barrier leakage current components.