This paper introduces a hybrid nine level inverter topology with extended dc bus utilisation for operation at over modulation range without the presence of lower order harmonics(predominantly 5th and 7th) when compared to conventional 2- level and multilevel inverter with hexagonal voltage Space Vector structure. The proposed inverter is a cascade of a five level Ttype unit and a H Bridge (HB) unit. An increase in the DC bus utilisation is possible by increasing the pole voltage levels to (Vdc=2+Vdc=8) using the H-bridge capacitor voltage and also the capacitor voltages are balanced by adding a offset to sine reference. The aforementioned PWM strategy allows to increase the peak phase fundamental voltage from 0:577Vdc to 0:625Vdc in case of unity power factor (p.f) load and to 0:637Vdc for 0.82 p.f load with the proposed nine level inverter. The limiting factor on increasing the DC bus utilisation such as power factor, HB capacitor balancing are analysed broadly in this paper. The proposed inverter scheme and its claim of increasing the peak phase fundamental voltage is experimentally validated in a laboratory prototype.

In this paper, a method is proposed, for the first time, to increase the linear modulation range till full base speed irrespective of load power factor for a multilevel inverter fed induction motor (IM) drive. A 5-level inverter with a single DC source is used for the proposed scheme. Using this method, linear PWM operation of the inverter can be achieved till peak phase fundamental voltage of 0.637Vdc without exceeding machine phase voltage rating. This method eliminates all the lower order harmonics from machine phase voltage till the full speed range of operation. The proposed 5-level inverter scheme is realized by cascading a 2-Level inverter with a capacitor fed H-Bridge, feeding Open-End Induction Motor (OEIM) drive from one end and a capacitor fed 2-Level inverter from the other end. The proposed scheme uses Space Vector (SV) redundancy to balance all the capacitors during its operation. Operation of the proposed drive is analyzed extensively for normal 5- Level operation as well as during the extended modulation range. Experimental results for steady state and transient state operation are presented to validate the proposed scheme.

With the integration of renewable energy sources into the power grid, a number of power electronic converters need to be connected together in parallel. Due to this interconnection among the power converters with a common DC bus, the equivalent impedance of the DC network, i.e., DC network impedance (DCNI) of these parallel converters, may vary and can cause oscillations in the DC link voltage (DCLV). In the literature, impedance models of grid-tied converters (GCs) based on the AC side are well reported without including these variations in DCNI. In addition, the dynamics of a phase-locked loop (PLL) play a significant role in GC system stability. To evaluate these stability issues, this paper proposes small signal impedance models viewing from the DC side of a three-phase GC operating under different control modes considering the PLL dynamics and the DCNI variations. Using the proposed DC impedance models (DCIM), DCLV stability analysis is evaluated for a GC. It is verified through bode plots that the interaction between the proposed DCIM and DCNI leads to unstable operation of the closed-loop converter near the PLL bandwidth when the phase difference between DCIM and DCNI is more than 180 degrees. Finally, the analytically developed models are validated using hardware in-the-loop (HIL) testing.

This article proposes a method of generating 24-sided polygonal voltage space vector structure composed of 24 real active vectors and a zero vector. Each active vector is a real vector in contrast to switched average vectors in literature. Generation of real 24-sided vectors minimizes switching losses and improves quality of phase voltage compared to switched averaged vectors technique. An important feature of the presented scheme is elimination of lower order harmonics up to 19th order from motor phase voltage throughout the modulation range that gives reduction in torque pulsation and near sinusoidal phase current. The proposed scheme extends the linear modulation range till 99.42$\%$. Open-end winding induction motor is fed with primary and secondary inverters from either ends. Primary and secondary inverters are implemented by cascading two-level inverters. DC sources for both the inverters are realized using a simple star-delta transformer combination. The proposed concepts are verified with laboratory prototype and the respective results during the steady-state, transient, and fault scenario are presented. The supporting loss analysis and harmonic performance of the proposed drive is performed with existing topologies.